公开(公告)号：US5428239A

公开(公告)日：1995-06-27

申请号：US71023

申请日：1993-06-03

申请人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

IPC分类号： H01L27/10 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/823892 ,  H01L21/76221 ,  H01L21/823493 ,  H01L27/10805 ,  H01L27/0928 ,  H01L27/105

摘要： A DRAM is formed on a silicon substrate having a retrograde well and a diffusion-type well. The retrograde well has an impurity concentration profile which is set in steps by a plurality of ion-implantations. The diffusion-type well has an impurity concentration profile which changes monotonously by a thermal diffusion. A memory cell array is formed in the retrograde well region. A peripheral circuit is formed in the diffusion-type well region. The retrograde well enhances integration of devices included in the memory cell array. The diffusion-type well enhances the characteristic of insulating isolation between devices.

摘要翻译： 在具有逆行阱和扩散型阱的硅衬底上形成DRAM。 逆行井具有通过多个离子注入步骤设置的杂质浓度分布。 扩散型阱具有通过热扩散单调变化的杂质浓度分布。 在逆行井区域中形成记忆单元阵列。 在扩散型阱区域中形成外围电路。 逆行井增强了存储单元阵列中包含的器件的集成。 扩散型井增强了器件之间绝缘隔离的特性。

公开(公告)号：US5404042A

公开(公告)日：1995-04-04

申请号：US71925

申请日：1993-06-04

申请人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Tomonori Okudaira ,  Hideaki Arima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L49/00 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/0218 ,  H01L27/105

摘要： A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.

摘要翻译： 根据本发明的半导体存储器件包括p型硅衬底中的多个n阱区和p阱区。 p个阱区中的一个连接到外部电源。 具有其中形成有存储单元阵列的p阱区的周边被具有保持在正电位的电位的n阱区围绕。 保持在正电位的n阱区防止由于下冲通过连接到外部电源的p阱区进入p阱区而引入到衬底中的电子。

公开(公告)号：US5164806A

公开(公告)日：1992-11-17

申请号：US698690

申请日：1991-05-13

申请人： Masao Nagatomo ,  Hiroki Shimano ,  Tomonori Okudaira ,  Yoshinori Okumura

发明人： Masao Nagatomo ,  Hiroki Shimano ,  Tomonori Okudaira ,  Yoshinori Okumura

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/765

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/76216 ,  H01L21/765 ,  H01L29/6656 ,  Y10S257/90

摘要： An element isolating structure employed for isolating the elements of a semiconductor substrate has an impurity region having a concentration lower than that of a source/drain and a channel stop region, between the source/drain of an MOS transistor formed in an active region, and the channel stop region formed under an LOCOS film.A field shield isolating structure has a low concentrated impurity region between the source/drain of an MOS transistor formed in the active region and the substrate surface region covered by a field shield electrode layer. The low concentrated impurity region improves its junction breakdown voltage in the boundary region with the element isolating region.An improved LOCOS film is formed into an amorphous region on the surface of the substrate by an oblique rotating ion implanting method, and the amorphous region is formed by thermal oxidation. The method suppresses the emergence of a bird's beak.

摘要翻译： 用于隔离半导体衬底的元件的元件隔离结构具有在有源区中形成的MOS晶体管的源极/漏极之间具有低于源极/漏极和沟道截止区域的浓度的杂质区域和 在LOCOS膜下形成的通道停止区域。 场屏蔽隔离结构在有源区中形成的MOS晶体管的源极/漏极与由场屏蔽电极层覆盖的衬底表面区域之间具有低浓度杂质区域。 低浓度杂质区域改善了与元件隔离区域的边界区域的结击穿电压。 通过倾斜旋转离子注入方法将改进的LOCOS膜形成在衬底的表面上的非晶区域中，通过热氧化形成非晶区域。 该方法抑制鸟喙的出现。

公开(公告)号：US5763921A

公开(公告)日：1998-06-09

申请号：US645700

申请日：1996-05-14

申请人： Yoshinori Okumura ,  Masahiko Takeuchi ,  Hideaki Arima

发明人： Yoshinori Okumura ,  Masahiko Takeuchi ,  Hideaki Arima

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/0928 ,  H01L21/823807

摘要： An n well and a p well are formed in a silicon substrate. The n well has n type impurity concentration peaks and a p type impurity concentration peak. The p well has p type concentration peaks. The impurity concentration peaks serving as channel stopper regions for isolating elements exist only in proximity to the lower surface of an isolation oxide film but not in element regions.

摘要翻译： 在硅衬底中形成n阱和p阱。 n阱具有n型杂质浓度峰和p型杂质浓度峰。 p阱具有p型浓度峰。 作为用于隔离元件的通道阻挡区域的杂质浓度峰值仅存在于隔离氧化膜的下表面附近，而不存在于元件区域中。

公开(公告)号：US5231041A

公开(公告)日：1993-07-27

申请号：US819206

申请日：1992-01-10

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层设置在它们之间，并且浮置栅极形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US5101250A

公开(公告)日：1992-03-31

申请号：US630439

申请日：1990-12-20

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层位于它们之间，浮栅形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US07554837B2

公开(公告)日：2009-06-30

申请号：US12213505

申请日：2008-06-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/10

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US06461920B1

公开(公告)日：2002-10-08

申请号：US09654877

申请日：2000-09-05

申请人： Masayoshi Shirahata ,  Yoshinori Okumura

发明人： Masayoshi Shirahata ,  Yoshinori Okumura

IPC分类号： H01L218236

CPC分类号： H01L21/26513 ,  H01L21/74 ,  H01L27/088 ,  H01L29/105

摘要： In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.

摘要翻译： 在半导体器件中，在半导体衬底的主表面上形成具有不同阈值的相同导电类型的多个MIS晶体管，并且在深度方向上从半导体衬底的主表面延伸通过各个沟道区域 多个MIS晶体管的峰值位于不同深度处。 该结构通过在具有不同注入能量或不同离子种类的各个沟道区上进行的离子注入形成。 根据该半导体器件，可以单独地控制MIS晶体管的阈值，并且可以获得对于使用最佳的晶体管特性。

公开(公告)号：US06399985B2

公开(公告)日：2002-06-04

申请号：US09750759

申请日：2001-01-02

申请人： Katsuyuki Horita ,  Takashi Kuroi ,  Yoshinori Okumura

发明人： Katsuyuki Horita ,  Takashi Kuroi ,  Yoshinori Okumura

IPC分类号： H01L2976

CPC分类号： H01L21/823481 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76235 ,  H01L27/0207 ,  H01L29/41758

摘要： Provided are a semiconductor device that can obtain more output current without increasing the occupied area of a MOS transistor, and a method for manufacturing the same. MOS transistors (M11, M12) are electrically isolated by a trench isolation oxide film (21). The MOS transistor (M11) has a groove portion (GP) in which the width of the top is 20 nm to 80 nm and the depth is 50 nm to 150 nm. The groove portion (GP) is disposed at the boundary part between a trench isolation insulating film (22) and an active region (AR1) so as to surround the active region (AR1). A gate electrode (31A) is not only disposed above the active region (AR1) but also buried in the groove (GP) with a gate oxide film (30) interposed therebetween. Similarly, in the MOS transistor (M12), a groove portion (GP) is disposed at the boundary part between the trench isolation insulating film (21) and an active region (AR2) so as to surround the active region (AR2), and a gate electrode (32A) is also buried in the groove (GP) with the gate oxide film (30) interposed therebetween.

摘要翻译： 提供一种可以在不增加MOS晶体管的占用面积的情况下获得更多的输出电流的半导体器件及其制造方法。 MOS晶体管（M11，M12）通过沟槽隔离氧化膜（21）电隔离。 MOS晶体管（M11）具有其顶部宽度为20nm〜80nm，深度为50nm〜150nm的槽部（GP）。 沟槽部分（GP）设置在沟道隔离绝缘膜（22）和有源区域（AR1）之间的边界部分，以围绕有源区域（AR1）。 栅电极（31A）不仅设置在有源区（AR1）的上方，而且还以栅介质膜（30）插入槽（GP）中。 类似地，在MOS晶体管（M12）中，沟槽部分（GP）设置在沟道隔离绝缘膜（21）和有源区域（AR2）之间的边界部分以包围有源区域（AR2），并且 栅极电极（32A）也被埋置在沟槽（GP）中，栅氧化膜（30）插入其间。

公开(公告)号：US06300656B1

公开(公告)日：2001-10-09

申请号：US08647532

申请日：1996-05-15

申请人： Shuichi Ueno ,  Shigeru Kusunoki ,  Yoshinori Okumura

发明人： Shuichi Ueno ,  Shigeru Kusunoki ,  Yoshinori Okumura

IPC分类号： G11C1134

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/66659 ,  H01L29/7835

摘要： A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

摘要翻译： 非易失性半导体存储器件包括在p型硅衬底的表面上与n +漏极扩散区域接触并覆盖其周围的n型区域。 该器件还包括与n型区域接触并覆盖其周边的p型​​杂质区域。 n +漏极扩散区域，n型区域和p +杂质区域延伸到位于浮置栅电极正下方的区域。 由此，非易失性半导体存储器件具有能够沿着栅电极方向注入高能电子的结构。