公开(公告)号：US20200294974A1

公开(公告)日：2020-09-17

申请号：US16889828

申请日：2020-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18

Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.

公开(公告)号：US10714452B2

公开(公告)日：2020-07-14

申请号：US15911180

申请日：2018-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18 ,  H01L23/31

Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.

公开(公告)号：US20180190623A1

公开(公告)日：2018-07-05

申请号：US15911180

申请日：2018-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.

公开(公告)号：US20160372410A1

公开(公告)日：2016-12-22

申请号：US15256749

申请日：2016-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L23/498 ,  H01L23/00 ,  H05K3/40 ,  C25D5/48 ,  H05K1/11 ,  C25D7/12 ,  C25D5/02 ,  C25D5/56 ,  H01L21/48 ,  H05K3/02

CPC classification number: H01L23/49822 ,  C25D5/02 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D5/56 ,  C25D7/12 ,  C25D7/123 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/80 ,  H01L24/96 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/80895 ,  H05K1/11 ,  H05K3/02 ,  H05K3/4007

Abstract: An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided.

Abstract translation: 插入器制造工艺包括以下步骤。 从底部到顶部堆叠基板，氧化物层和电介质层，并且提供介电层中的互连，其中介电层包括与氧化物层接触的阻挡层，并且互连件包括具有阻挡层的金属结构 层从停止层突出。 去除衬底和氧化物层，直到通过氧化物层和停止层之间的去除选择性露出阻挡层和阻挡层。 还提供了由所述插入件形成的晶片封装结构。

公开(公告)号：US20150179580A1

公开(公告)日：2015-06-25

申请号：US14139879

申请日：2013-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist.

Abstract translation: 公开了一种用于制造混合互连结构的方法。 该方法包括以下步骤：提供材料层; 在所述材料层中形成通孔; 在所述材料层上形成图案化的抗蚀剂，其中所述图案化的抗蚀剂至少包括用于暴露所述通孔的孔; 以及形成导电层以填充图案化的抗蚀剂中的通孔和孔。

公开(公告)号：US09024416B2

公开(公告)日：2015-05-05

申请号：US13964184

申请日：2013-08-12

Applicant: United Microelectronics Corp.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin ,  Chien-Li Kuo ,  Kuei-Sheng Wu

IPC: H01L23/552 ,  H01L21/00 ,  H01L23/60 ,  H01L49/02 ,  H01L23/14 ,  H01L23/498 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L23/60 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.

Abstract translation: 提供半导体结构。 半导体结构包括内插器结构。 插入器结构包括插入器衬底，接地，通孔，电介质层和电感器。 通孔形成在插入器基板中并电连接到地。 介电层位于内插器基板上。 电感在介质层上。

公开(公告)号：US20150061151A1

公开(公告)日：2015-03-05

申请号：US14016330

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/522

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package structure having silicon through vias connected to ground potential is disclosed, comprising a first device, a second device and a conductive adhesive disposed between the first device and the second device. The first device comprises a substrate having a front surface and a back surface, and a plurality of through silicon vias filled with a conductor formed within the substrate. The first device is externally connected to the second device by wire bonding.

Abstract translation: 公开了一种具有连接到地电势的硅通孔的封装结构，包括设置在第一器件和第二器件之间的第一器件，第二器件和导电粘合剂。 第一器件包括具有前表面和后表面的衬底以及填充有形成在衬底内的导体的多个通孔硅通孔。 第一器件通过引线接合外部连接到第二器件。

公开(公告)号：US09666507B2

公开(公告)日：2017-05-30

申请号：US14556215

申请日：2014-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chien-Li Kuo ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating through-substrate structure is disclosed. The method includes the steps of: providing a substrate; forming a through-substrate hole and a through-substrate trench in the substrate; and forming a metal layer in the through-substrate hole and the through-substrate trench for forming a through-substrate via and a through-substrate conductor having a void therein.

公开(公告)号：US09343359B2

公开(公告)日：2016-05-17

申请号：US14140523

申请日：2013-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin ,  Chien-Li Kuo

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/525

CPC classification number: H01L21/76879 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

Abstract translation: 公开了一种制造一体化结构的方法。 该方法包括以下步骤：提供衬底; 在所述基板中形成贯通硅孔; 在衬底上形成图案化的抗蚀剂，其中所述图案化抗蚀剂包括对应于再分布层（RDL）图案的至少一个开口，并暴露所述穿硅孔和至少另一个对应于另一再分布层（RDL）图案的开口，并连接到 所述至少一个开口; 以及形成导电层以填充图案化的抗蚀剂中的通孔，至少一个开口和至少另一个开口，以便形成贯穿硅通孔，穿硅通孔RDL图案和另一RDL图案 一个结构。

公开(公告)号：US20150348892A1

公开(公告)日：2015-12-03

申请号：US14289630

申请日：2014-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L23/498 ,  C25D5/34 ,  C25D5/48 ,  H01L21/48 ,  C25D5/02

CPC classification number: H01L23/49822 ,  C25D5/02 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D5/56 ,  C25D7/12 ,  C25D7/123 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/80 ,  H01L24/96 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/80895 ,  H05K1/11 ,  H05K3/02 ,  H05K3/4007

Abstract: An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided.

Abstract translation: 插入器制造工艺包括以下步骤。 从底部到顶部堆叠基板，氧化物层和电介质层，并且提供介电层中的互连，其中介电层包括与氧化物层接触的阻挡层，并且互连件包括具有阻挡层的金属结构 层从停止层突出。 去除衬底和氧化物层，直到通过氧化物层和停止层之间的去除选择性露出阻挡层和阻挡层。 还提供了由所述插入件形成的晶片封装结构。