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公开(公告)号：US20180342425A1
公开(公告)日：2018-11-29
申请号：US16038196
申请日：2018-07-18
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Ming-Feng Kuo , Li-Chiang Chen
IPC: H01L21/8234 , H01L27/108
Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.
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公开(公告)号：US20180335703A1
公开(公告)日：2018-11-22
申请号：US15937825
申请日：2018-03-27
Inventor： Ying-Chiao Wang , Yu-Cheng Tung , Li-Wei Feng , Chien-Ting Ho
Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n−1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.
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公开(公告)号：US10121790B2
公开(公告)日：2018-11-06
申请号：US15802472
申请日：2017-11-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Yu-Cheng Tung
IPC: H01L27/092 , H01L21/8238 , H01L27/088 , H01L21/02 , H01L21/8234 , H01L21/225 , H01L29/66
Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.
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公开(公告)号：US10103062B2
公开(公告)日：2018-10-16
申请号：US14814516
申请日：2015-07-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Chao-Hung Lin , Yu-Cheng Tung
IPC: H01L21/8234 , H01L21/762 , H01L27/088 , H01L21/308 , H01L29/06 , H01L21/28
Abstract: A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a top surface of the substrate, the substrate including a first recess and a second recess disposed under the first recess, and the first recess and the second recess being disposed between the fin structures, wherein a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure; forming an insulating structure in the second recess; and forming the gate structure on the insulating structure, wherein the first recess and the second recess are filled up with the gate structure and the insulating structure.
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公开(公告)号：US20180284596A1
公开(公告)日：2018-10-04
申请号：US15585000
申请日：2017-05-02
Applicant: United Microelectronics Corp.
Inventor： En-Chiuan Liou , Yu-Cheng Tung
Abstract: An extreme ultraviolet (EUV) photomask includes a mask substrate, a reflection layer and a light-absorbing pattern layer. The reflection layer is disposed on the mask substrate, wherein the reflection layer has a concave pattern. The light-absorbing pattern layer is in the reflection layer, to fill the concave pattern. The light-absorbing pattern layer is exposed.
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Patent Agency Ranking
公开(公告)号：US10068969B2
公开(公告)日：2018-09-04
申请号：US15146898
申请日：2016-05-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Cheng Tung
IPC: H01L29/06 , H01L29/16 , H01L29/49 , H01L23/535 , H01L29/786 , H01L29/66 , H01L21/306
Abstract: A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made of different material. Next, a hard mask is formed on the stack structure and a first spacer adjacent to the hard mask, part of the stack structure is removed; a second spacer is formed adjacent to the first spacer and the stack structure; and a source/drain structure is formed adjacent to two sides of the second spacer.
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公开(公告)号：US10056463B2
公开(公告)日：2018-08-21
申请号：US15628592
申请日：2017-06-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Su Xing , Hsueh-Wen Wang , Chien-Yu Ko , Yu-Cheng Tung , Jen-Yu Wang , Cheng-Tung Huang , Yu-Ming Lin
IPC: H01L21/28 , H01L29/51 , H01L29/786 , H01L29/66 , H01L27/11585
CPC classification number: H01L29/516 , H01L27/11585 , H01L29/40111 , H01L29/42376 , H01L29/4908 , H01L29/66545 , H01L29/6684 , H01L29/66969 , H01L29/7869
Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.
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公开(公告)号：US09991337B2
公开(公告)日：2018-06-05
申请号：US14840038
申请日：2015-08-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Chih-Wei Yang , Yu-Cheng Tung , Chun-Yuan Wu
IPC: H01L29/06 , H01L29/66 , H01L29/78 , H01L21/762 , H01L21/308 , H01L21/311 , H01L21/283
CPC classification number: H01L29/0649 , H01L21/283 , H01L21/3081 , H01L21/31144 , H01L21/76232 , H01L29/66795 , H01L29/785
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.
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公开(公告)号：US09971250B2
公开(公告)日：2018-05-15
申请号：US14534190
申请日：2014-11-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Cheng Tung
CPC classification number: G03F7/70466 , G03F1/70
Abstract: A method of decomposing layout design for preparing a photomask set printed onto a wafer by photolithography includes the following steps. An integrated circuit layout design including several features is obtained. The overlay relation of these features is recognized to classify these features into a first group and a second group. These features printed onto different layers of the wafer are distinguished to decompose the first group into a first feature and a third feature, and the second group into a second feature and a fourth feature. The first feature is outputted to a first photomask, the second feature is outputted to a second photomask, a third feature is outputted to a third photomask and a fourth feature is outputted to a fourth photomask. A method of forming a photomask set and a method of fabricating an integrated circuit are also provided.
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公开(公告)号：US09922834B2
公开(公告)日：2018-03-20
申请号：US14820565
申请日：2015-08-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Yu-Cheng Tung
IPC: H01L29/66 , H01L29/06 , H01L21/283 , H01L21/308 , H01L21/31 , H01L21/762 , H01L29/78 , H01L29/10 , H01L21/8234 , H01L21/84
CPC classification number: H01L21/283 , H01L21/308 , H01L21/31 , H01L21/76224 , H01L21/823431 , H01L21/845
Abstract: A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.
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