公开(公告)号：US09136375B2

公开(公告)日：2015-09-15

申请号：US14085939

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

公开(公告)号：US20150137228A1

公开(公告)日：2015-05-21

申请号：US14085939

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

公开(公告)号：US08829611B2

公开(公告)日：2014-09-09

申请号：US13629608

申请日：2012-09-28

Applicant: United Microelectronics Corp.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/78

CPC classification number: H01L29/0878 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7816

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高电压金属氧化物半导体晶体管器件包括其中形成有绝缘区域的衬底，覆盖绝缘区域的一部分并形成在衬底上的栅极，形成在栅极各侧的源极区域和漏极区域 基板，形成在基板中并与栅极部分重叠的主体区域，以及形成在栅极下方并与主体区域相邻的基板中的第一注入区域。 衬底和体区包括第一导电类型。 源极区域，漏极区域和第一注入区域包括第二导电类型。 第一导电类型和第二导电类型彼此互补。

公开(公告)号：US11804526B2

公开(公告)日：2023-10-31

申请号：US17895066

申请日：2022-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

IPC: H01L29/76 ,  H01L31/062 ,  H01L29/94 ,  H01L29/40 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L27/088 ,  H01L29/7816

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

公开(公告)号：US20220406903A1

公开(公告)日：2022-12-22

申请号：US17895054

申请日：2022-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

IPC: H01L29/40 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

公开(公告)号：US11462621B2

公开(公告)日：2022-10-04

申请号：US17200908

申请日：2021-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

IPC: H01L29/76 ,  H01L31/062 ,  H01L29/40 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

公开(公告)号：US11417761B1

公开(公告)日：2022-08-16

申请号：US17171760

申请日：2021-02-09

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

公开(公告)号：US20220254924A1

公开(公告)日：2022-08-11

申请号：US17171760

申请日：2021-02-09

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substrate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

公开(公告)号：US20220254888A1

公开(公告)日：2022-08-11

申请号：US17200908

申请日：2021-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chieh Wang ,  Po-Chun Lai ,  Ke-Feng Lin ,  Chen-An Kuo ,  Ze-Wei Jhou

IPC: H01L29/40 ,  H01L29/78 ,  H01L27/088

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.

公开(公告)号：US10276652B1

公开(公告)日：2019-04-30

申请号：US16005652

申请日：2018-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Ke-Feng Lin ,  Ming-Tsung Lee ,  Shih-Teng Huang ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shu-Wen Lin

IPC: H01L29/06 ,  H01L29/872

Abstract: A schottky diode includes a schottky junction, an ohmic junction, a first isolation structure and a plurality of doped regions. The schottky junction includes a first well in a substrate and a first electrode contacting the first well. The ohmic junction includes a junction region in the first well and a second electrode contacting the junction region. The first isolation structure is disposed in the substrate and separates the schottky junction from the ohmic junction. The doped regions are located in the first well and under the schottky junction, wherein the doped regions separating from each other constitute a top-view profile of concentric circles.