公开(公告)号：US20180269212A1

公开(公告)日：2018-09-20

申请号：US15491939

申请日：2017-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/11 ,  H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66484 ,  H01L29/7831

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate includes a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.

公开(公告)号：US09837497B1

公开(公告)日：2017-12-05

申请号：US15296045

申请日：2016-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/306 ,  H01L29/786 ,  H01L29/76 ,  H01L29/423 ,  H01L29/34 ,  H01L29/06 ,  H01L29/20 ,  H01L29/24 ,  H01L21/308

CPC classification number: H01L29/34 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0692 ,  H01L29/20 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/785

Abstract: A channel structure includes a first patterned channel layer including a lower portion and an upper portion. The upper portion is disposed on the lower portion. A width of the upper portion is larger than a width of the lower portion. A material or a material composition ratio of the upper portion is different from a material or a material composition ratio of the lower portion. The height and the channel length of the channel structure are increased by disposing the first patterned channel layer, and the saturation current (Isat) of a transistor including the channel structure of the present invention may be enhanced accordingly.

公开(公告)号：US11804550B2

公开(公告)日：2023-10-31

申请号：US17705376

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78603 ,  H01L21/2253 ,  H01L21/762 ,  H01L21/8232 ,  H01L29/0653 ,  H01L29/66772 ,  H01L29/749

Abstract: A method for fabricating a field-effect transistor includes the following steps. A gate structure layer in a line shape including a first region and a second region abutting to the first region is formed on a silicon layer. A first implanting process is performed to implant first-type dopants at least into a second portion of the second region of the gate structure layer. A second implanting region is performed to implant second-type dopants into the silicon layer to form a source region and a second region corresponding to the first region of the gate structure layer. The gate structure layer has a conductive-type junction at an interface between the first and second portions of the second region. A width of the silicon layer under the second region of the gate structure layer is smaller than a width of the gate structure layer.

公开(公告)号：US11799031B2

公开(公告)日：2023-10-24

申请号：US17705380

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L21/8232 ,  H01L21/762 ,  H01L29/749 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225

CPC classification number: H01L29/78603 ,  H01L21/2253 ,  H01L21/762 ,  H01L21/8232 ,  H01L29/0653 ,  H01L29/66772 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20220270973A1

公开(公告)日：2022-08-25

申请号：US17204966

申请日：2021-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Su Xing ,  Shyam Parthasarathy

IPC: H01L23/538 ,  H01L25/065 ,  H01L27/06 ,  H01L23/552 ,  H01L21/50 ,  H01L21/768

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device wafer includes a first insulating layer, a first device layer on the first insulating layer, and a first bonding layer on the first device layer. The second device wafer includes a second insulating layer, a second device layer on a first side of the second insulating layer, and a second bonding layer on the second device layer. The second device layer includes a second device region and a second transistor in the second device region. The second device wafer is bonded to the first device wafer by bonding the second bonding layer with the first bonding layer. A shielding structure is on a second side of the second insulating layer opposite to the first side and vertically overlapped with the second device region.

公开(公告)号：US20220216344A1

公开(公告)日：2022-07-07

申请号：US17705376

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US10978556B2

公开(公告)日：2021-04-13

申请号：US16280047

申请日：2019-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10 ,  H01L29/49

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.

公开(公告)号：US10347645B2

公开(公告)日：2019-07-09

申请号：US16207171

申请日：2018-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L27/11 ,  H01L27/12 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate comprises a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.

公开(公告)号：US10290641B1

公开(公告)日：2019-05-14

申请号：US15871920

申请日：2018-01-15

Applicant: United Microelectronics Corp.

Inventor： Wan-Xun He ,  Su Xing

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12

Abstract: A semiconductor device has a 6T SRAM cell formed on a substrate. The SRAM cell includes a first and a second PMOS transistors formed over an N-well line in a substrate. A first and a second NMOS transistors are formed over a first P-well line in the substrate at a first side of the N-well line. A third and a fourth NMOS transistors are formed over a second P-well line in the substrate at a second side of the N-well line. A first gate line connects gates of the first PMOS transistor and the first NMOS transistor. A second gate line connects a gate of the second NMOS transistor. A third gate line connects gates of the second PMOS transistor and the third NMOS transistor. A fourth gate line connects a gate of the fourth NMOS transistor. The first gate line and the third gate line are in L-shape.

公开(公告)号：US10062701B2

公开(公告)日：2018-08-28

申请号：US15361070

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1116

Abstract: The present invention provides a SRAM unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. The first well is disposed in the semiconductor substrate, and the first well has a first conductive type, wherein the first gate line and the second gate line extend onto the first well. The first doped regions are disposed in the first well at two sides of the first gate line, and the second doped regions are disposed in the first well at two sides of the second gate line.