公开(公告)号：US10243084B2

公开(公告)日：2019-03-26

申请号：US15279410

申请日：2016-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L29/423

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.

公开(公告)号：US09564520B1

公开(公告)日：2017-02-07

申请号：US15199684

申请日：2016-06-30

Applicant: United Microelectronics Corp.

Inventor： Tzu-Ping Chen

IPC: H01L29/66 ,  H01L27/115 ,  H01L21/311

CPC classification number: H01L29/66833 ,  H01L21/0331 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/1157 ,  H01L29/4234

Abstract: A method of forming a semiconductor device is disclosed. A sacrificial oxide layer is formed on a substrate having first and second areas. Using a photoresist mask exposing the first area and covering the second area as a mask layer, by a wet etching process, the sacrificial oxide layer in the first area and an edge portion of the sacrificial oxide layer in the second area are simultaneously removed, wherein the sacrificial oxide layer remained in the second area has a sidewall with a slope smaller than 40 degrees. An oxide-nitride-oxide (ONO) layer is formed over the first and second areas. The sacrificial oxide layer and the ONO layer formed thereon in the second area are removed, so that the ONO layer remained in the first area forms a first gate insulating layer in the first area. A second gate insulating layer is formed in the second area.

Abstract translation: 公开了一种形成半导体器件的方法。 在具有第一和第二区域的基板上形成牺牲氧化物层。 使用暴露第一区域并覆盖第二区域作为掩模层的光致抗蚀剂掩模，通过湿蚀刻工艺，同时去除第一区域中的牺牲氧化物层和第二区域中的牺牲氧化物层的边缘部分，其中 残留在第二区域中的牺牲氧化物层具有斜率小于40度的侧壁。 在第一和第二区域上形成氧化物 - 氧化物 - 氧化物（ONO）层。 去除在第二区域中形成在其上的牺牲氧化物层和ONO层，使得残留在第一区域中的ONO层在第一区域中形成第一栅极绝缘层。 第二栅极绝缘层形成在第二区域中。

公开(公告)号：US09490016B2

公开(公告)日：2016-11-08

申请号：US14489439

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L29/788 ,  G11C16/14 ,  H01L29/66 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  H01L27/115

CPC classification number: H01L29/7887 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a floating gate on the substrate; a first silicon oxide layer between the floating gate and the substrate; a first tunnel oxide layer and a second tunnel oxide layer adjacent to two sides of the first silicon oxide layer; and a control gate on the floating gate. Preferably, the thickness of the first tunnel oxide layer and the second tunnel oxide layer is less than the thickness of the first silicon oxide layer.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 衬底上的浮动栅极; 在浮置栅极和衬底之间的第一氧化硅层; 与第一氧化硅层的两侧相邻的第一隧道氧化物层和第二隧道氧化物层; 和浮动门上的控制门。 优选地，第一隧道氧化物层和第二隧道氧化物层的厚度小于第一氧化硅层的厚度。

公开(公告)号：US20160079380A1

公开(公告)日：2016-03-17

申请号：US14488295

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Yi Tseng ,  Tzu-Ping Chen ,  Chun-Lung Chang ,  Chih-Haw Lee ,  Wei-Shiang Huang ,  Chien-Hung Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L21/28035 ,  H01L21/28158 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

Abstract translation: 提供了栅极结构。 栅极结构包括衬底，设置在衬底上的栅极和设置在衬底和栅极之间的栅极电介质层，其中栅极电介质层为杠铃形状。 杠铃具有连接到两个凸起端的薄中心。 凸出部分的一部分延伸到栅极和衬底中。

公开(公告)号：US20150333130A1

公开(公告)日：2015-11-19

申请号：US14277784

申请日：2014-05-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen

IPC: H01L29/40 ,  H01L21/28

CPC classification number: H01L29/401 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/11568 ,  H01L27/11573

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of first providing a substrate, in which the substrate includes a SONOS region and a EEPROM region. Next, a first gate layer is formed in the SONOS region and the EEPROM region, the first gate layer is patterned by removing the first gate layer from the SONOS region and forming a floating gate pattern in the EEPROM region, an ONO layer is formed in the SONOS region and the EEPROM region, a second gate layer is formed on the ONO layer of the SONOS region and the EEPROM region, the second gate layer and the first gate layer are patterned to form a floating gate and a control gate in the EEPROM region, and the second gate layer is patterned to form a first gate in the SONOS region.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：首先提供衬底，其中衬底包括SONOS区域和EEPROM区域。 接下来，在SONOS区域和EEPROM区域中形成第一栅极层，通过从SONOS区域移除第一栅极层并在EEPROM区域中形成浮置栅极图案来对第一栅极层进行图案化，形成ONO层 SONOS区域和EEPROM区域，在SONOS区域的ONO层上形成第二栅极层，对EEPROM区域，第二栅极层和第一栅极层进行图案化以在EEPROM中形成浮置栅极和控制栅极 区域，并且第二栅极层被图案化以在SONOS区域中形成第一栅极。