公开(公告)号：US20210183944A1

公开(公告)日：2021-06-17

申请号：US16746974

申请日：2020-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jian-Jhong Chen ,  Po-Chun Yang ,  Jhen-Siang Wu ,  Yung-Ching Hsieh ,  Bo-Chang Li ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.

公开(公告)号：US09632115B2

公开(公告)日：2017-04-25

申请号：US13894021

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Tsung-Han Lee ,  Yi-Han Ye

IPC: G01R19/00 ,  G01R31/26

CPC classification number: G01R19/0084 ,  G01R31/2621

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ηk values is provided. A set of VBi values (i=1 to M, M≧3) is provided. A set of RSDi,j (i=1 to M−1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq_q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ηk, with an iteration method. The ηk value making the set of RSDi,j values or Vtq_q,j values closest to each other is determined as an accurate ηk value. The mean value of RSDi,j at the accurate ηk value is calculated as an accurate RSD value.

公开(公告)号：US20170040346A1

公开(公告)日：2017-02-09

申请号：US15296027

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Ya-Ru Yang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/308 ,  H01L29/165 ,  H01L29/16 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3081 ,  H01L21/76251 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract translation: 一种制造半导体器件的衬底的方法包括以下步骤：提供第一硅层; 在所述第一硅层上形成介电层; 将第二硅层接合到介电层; 去除所述第二硅层的一部分和所述介电层的一部分以限定所述第一硅层上的第一区域和第二区域，其中所述第二硅层和所述介电层的剩余部分位于所述第二区域上; 以及在所述第一硅层的所述第一区上形成外延层，其中所述外延层和所述第二硅层包含相同的晶体取向。

公开(公告)号：US20250078891A1

公开(公告)日：2025-03-06

申请号：US18950204

申请日：2024-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Jia-Rong Wu ,  Yi-Ting Wu

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.

公开(公告)号：US20240203471A1

公开(公告)日：2024-06-20

申请号：US18108025

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Jia-Rong Wu ,  Yi-Ting Wu

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H10B61/20 ,  H10N50/10

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.

公开(公告)号：US20230343379A1

公开(公告)日：2023-10-26

申请号：US17744746

申请日：2022-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Tung Huang ,  Jen-Yu Wang ,  Po-Chun Yang ,  Yi-Ting Wu ,  Yung-Ching Hsieh ,  Jian-Jhong Chen ,  Chia-Wei Lee

IPC: G11C11/16

CPC classification number: G11C11/1673

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

公开(公告)号：US20230282261A1

公开(公告)日：2023-09-07

申请号：US17707934

申请日：2022-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Jen-Yu Wang ,  Li-Ping Huang ,  Yi-Ting Wu ,  Jia-Rong Wu ,  Chun-Hsien Huang

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

公开(公告)号：US20220384523A1

公开(公告)日：2022-12-01

申请号：US17368848

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Jen-Yu Wang ,  Yung-Ching Hsieh ,  Po-Chun Yang ,  Jian-Jhong Chen ,  Bo-Chang Li

IPC: H01L27/22 ,  H01L43/02

Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

公开(公告)号：US11489010B2

公开(公告)日：2022-11-01

申请号：US17006928

申请日：2020-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Shu-Ru Wang ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Yi-Ting Wu ,  Shu-Wei Yeh ,  Ya-Lan Chiou ,  Chun-Hsien Huang

IPC: H01L27/22 ,  H01L43/02

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

公开(公告)号：US11018185B1

公开(公告)日：2021-05-25

申请号：US16746974

申请日：2020-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jian-Jhong Chen ,  Po-Chun Yang ,  Jhen-Siang Wu ,  Yung-Ching Hsieh ,  Bo-Chang Li ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.