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公开(公告)号:US10916694B2
公开(公告)日:2021-02-09
申请号:US16255754
申请日:2019-01-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L43/08 , H01L41/47 , H01L21/768 , H01L43/02 , H01L21/762
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
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公开(公告)号:US20210028352A1
公开(公告)日:2021-01-28
申请号:US17064614
申请日:2020-10-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Kuo , Meng-Jun Wang , Yi-Wei Tseng , Yu-Tsung Lai , Jiunn-Hsiung Liao
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.
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公开(公告)号:US20210020828A1
公开(公告)日:2021-01-21
申请号:US16531129
申请日:2019-08-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号:US20210020693A1
公开(公告)日:2021-01-21
申请号:US16544923
申请日:2019-08-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Kuo , Tai-Cheng Hou , Yu-Tsung Lai , Jiunn-Hsiung Liao
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
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公开(公告)号:US20200212290A1
公开(公告)日:2020-07-02
申请号:US16255754
申请日:2019-01-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L41/47 , H01L21/762 , H01L43/02 , H01L21/768
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
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公开(公告)号:US20190096748A1
公开(公告)日:2019-03-28
申请号:US15712153
申请日:2017-09-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Wei Kuo , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC: H01L21/768
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.
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公开(公告)号:US09230812B2
公开(公告)日:2016-01-05
申请号:US13899577
申请日:2013-05-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chieh-Te Chen , Yu-Tsung Lai , Hsuan-Hsu Chen , Feng-Yi Chang
IPC: H01L21/311 , H01L21/28 , H01L21/768 , H01L21/033
CPC classification number: H01L21/28 , H01L21/0332 , H01L21/31144 , H01L21/76816
Abstract: A method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. A pattern density of the first region is substantially greater than that of the second region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.
Abstract translation: 提供一种形成具有开口的半导体结构的方法。 首先,提供衬底,其中在衬底上限定第一区域和第二区域,并且将第一区域和第二区域的重叠区域定义为第三区域。 第一区域的图案密度基本上大于第二区域的图案密度。 然后,在基板上形成材料层。 第一硬掩模和第二硬掩模形成在材料层上。 第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。 去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。 最后,通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化,以仅在第三区域中形成至少一个开口。
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公开(公告)号:US20230403946A1
公开(公告)日:2023-12-14
申请号:US18239079
申请日:2023-08-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Laio , Yu-Tsung Lai , Wei-Hao Huang
IPC: H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80
CPC classification number: H10N50/10 , H01L21/76802 , H01L21/762 , H10N50/80 , H10N35/01
Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
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公开(公告)号:US11706993B2
公开(公告)日:2023-07-18
申请号:US17134460
申请日:2020-12-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L43/12 , H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80 , H10N35/01
CPC classification number: H10N50/10 , H01L21/762 , H01L21/76802 , H10N50/80 , H10N35/01
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
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公开(公告)号:US20220085283A1
公开(公告)日:2022-03-17
申请号:US17533003
申请日:2021-11-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L43/08 , H01L21/768 , H01L43/02 , H01L21/762
Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
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