公开(公告)号：US20110027951A1

公开(公告)日：2011-02-03

申请号：US12902944

申请日：2010-10-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/8234

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US20100330756A1

公开(公告)日：2010-12-30

申请号：US12491270

申请日：2009-06-25

申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes

发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807

摘要： A method of manufacturing an integrated circuit structure implants a first-type of channel implant in a first area of a substrate and implants a second-type of channel implant in a second area of the substrate. The method forms at least one first gate conductor above the first area of the substrate and forms at least one second gate conductor above the second area of the substrate. The method forms a hard mask over the first gate conductor, the second gate conductor, and the substrate. The hard mask comprises an oxide or a nitride and patterns an organic photoresist over the hard mask, to leave the organic photoresist on areas of the hard mask that are above the first area of the substrate. The method removes portions of the hard mask not protected by the organic photoresist to leave the hard mask on the first area of the substrate and not on the second area of the substrate. The method then removes the organic photoresist, implants impurities in the second area of the substrate to form source and drain regions adjacent the second gate conductor; and removes the hard mask using a wet etching process.

摘要翻译： 一种制造集成电路结构的方法是将衬底的第一区域中的第一种沟道注入植入，并在衬底的第二区域中注入第二类沟道注入。 该方法在衬底的第一区域之上形成至少一个第一栅极导体，并在衬底的第二区域上方形成至少一个第二栅极导体。 该方法在第一栅极导体，第二栅极导体和衬底上形成硬掩模。 硬掩模包括氧化物或氮化物，并且在硬掩模上形成有机光致抗蚀剂，以将有机光致抗蚀剂留在位于衬底的第一区域上方的硬掩模的区域上。 该方法除去未被有机光致抗蚀剂保护的硬掩模的部分，以将硬掩模留在衬底的第一区域上，而不在衬底的第二区域上。 该方法然后去除有机光致抗蚀剂，在衬底的第二区域内植入杂质以形成邻近第二栅极导体的源区和漏区; 并使用湿蚀刻工艺去除硬掩模。

公开(公告)号：US07652334B2

公开(公告)日：2010-01-26

申请号：US11866471

申请日：2007-10-03

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/72

CPC分类号： H01L21/02164 ,  H01L21/0214 ,  H01L21/02282 ,  H01L21/3143 ,  H01L21/3147 ,  H01L21/316 ,  H01L21/76224 ,  H01L21/823878

摘要： A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.

摘要翻译： 一种用于形成半导体结构的方法和结构。 提供半导体衬底。 在半导体衬底内形成沟槽。 第一层电绝缘材料形成在沟槽内。 去除第一层电绝缘材料的第一部分和第二部分。 选择性地在第一层上生长第二层电绝缘材料，该第一层包括去除的第一部分和被去除的第二部分。

公开(公告)号：US07521808B2

公开(公告)日：2009-04-21

申请号：US11745610

申请日：2007-05-08

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L28/528

CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76874 ,  H01L23/5283 ,  H01L23/53209 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

摘要翻译： 使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。 金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。 然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

公开(公告)号：US20090072317A1

公开(公告)日：2009-03-19

申请号：US12273894

申请日：2008-11-19

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

公开(公告)号：US20090057730A1

公开(公告)日：2009-03-05

申请号：US11850172

申请日：2007-09-05

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume, depositing a liner layer on the substrate, the spacers, and the gate conductor stack, depositing a dielectric layer on the liner layer, etching to form a contact hole in the dielectric layer, etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed and depositing contact metal in the contact hole.

摘要翻译： 一种用于形成半导体FET（场效应晶体管）器件的无边界接触的方法，所述方法包括：在衬底上形成栅极导体堆叠，在衬底上形成间隔物，使得间隔物和栅极导体堆叠部分地限定体积 在栅极导体堆叠之上，其中间隔物的尺寸设定成限定体积，使得沉积在栅极导体堆叠上的应力衬垫层基本上填充体积，在衬底，间隔物和栅极导体堆叠上沉积衬垫层，沉积 衬底层上的电介质层，蚀刻以在电介质层中形成接触孔，蚀刻以在衬垫层中形成接触孔，使得在衬底中形成的源极/漏极扩散区域的一部分被暴露并沉积接触 接触孔中的金属。

公开(公告)号：US07439144B2

公开(公告)日：2008-10-21

申请号：US11307671

申请日：2006-02-16

申请人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/8222 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/823828 ,  H01L21/823864

摘要： A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the polymer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

摘要翻译： 用于形成亚光刻结构的侧壁图像转印工艺使用沉积在栅极导体层上并被覆盖层覆盖的含有硅的牺牲聚合物层。 牺牲聚合物层用常规抗蚀剂图案化并蚀刻以形成牺牲心轴。 心轴的边缘在低温下在等离子体中被氧化或氮化，之后剥离聚合物和覆盖层，留下亚光刻的侧壁。 侧壁用作硬掩模来蚀刻栅极导体层中的亚光刻栅极结构。

公开(公告)号：US20080165335A1

公开(公告)日：2008-07-10

申请号：US12051572

申请日：2008-03-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Peter H. Mitchell

IPC分类号： G03B27/42

CPC分类号： G03F7/70341

摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.

摘要翻译： 公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。 特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要 用于特殊镜头。 此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

公开(公告)号：US07352030B2

公开(公告)日：2008-04-01

申请号：US11374939

申请日：2006-03-14

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L27/01

CPC分类号： H01L29/0653 ,  B82Y10/00 ,  H01L21/28114 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654 ,  H01L29/78684

摘要： Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.

摘要翻译： 半导体结构和形成半导体结构的方法。 包括纳米结构或使用纳米结构制造的半导体结构。 形成半导体结构的方法包括使用纳米掩模生成纳米结构，并使用所生成的纳米结构进行附加的半导体加工步骤。

公开(公告)号：US20070296937A1

公开(公告)日：2007-12-27

申请号：US11426458

申请日：2006-06-26

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Peter H. Mitchell

IPC分类号： G03B27/42

CPC分类号： G03B27/42 ,  G03F7/70341 ,  G03F7/7085 ,  G03F7/70916

摘要： Embodiments of the invention present a system, method, etc. for illumination light in an immersion lithography stepper for particle or bubble detection. More specifically, embodiments herein provide an immersion lithography expose system comprising a wafer holder for holding a wafer, an immersion liquid for covering the wafer, an immersion head to dispense and contain said immersion liquid, and a light source adapted to lithographically expose a resist on the wafer. The system also comprises a light detector at a first location of the immersion head and a laser source at a second location within said immersion head.

摘要翻译： 本发明的实施例在用于颗粒或气泡检测的浸没式光刻步进机中提供照明光的系统，方法等。 更具体地，本文的实施例提供了浸没式光刻曝光系统，其包括用于保持晶片的晶片保持器，用于覆盖晶片的浸没液体，用于分配和容纳所述浸没液体的浸没头，以及适于光刻曝光抗蚀剂的光源 晶圆。 该系统还包括在浸没头的第一位置处的光检测器和位于所述浸没头内的第二位置处的激光源。