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    Methods for Forming Field Effect Transistor Devices With Protective Spacers
    1.
    发明申请
    Methods for Forming Field Effect Transistor Devices With Protective Spacers 审中-公开
    用保护隔离层形成场效应晶体管器件的方法

    公开(公告)号：US20120181613A1

    公开(公告)日：2012-07-19

    申请号：US13009271

    申请日：2011-01-19

    申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Sivananda K. Kanakasabapathy

    发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Sivananda K. Kanakasabapathy

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238

    CPC分类号： H01L29/66477 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/78

    摘要： A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer.

    摘要翻译： 一种用于形成场效应晶体管器件的方法包括在衬底上形成第一栅极堆叠和第二栅极叠层，在第二栅极堆叠上沉积第一光致抗蚀剂材料和衬底的一部分，将衬底的暴露区域中的离子注入到 限定与第一栅极堆叠相邻的第一源极区域和第一漏极区域，在第一源极区域，第一栅极堆叠层，第一漏极区域和第一光致抗蚀剂材料上沉积第一保护层，去除第一保护层 以露出第一光致抗蚀剂材料并且限定设置在第一源极区域和第一漏极区域的一部分上的第一间隔物，去除第一光致抗蚀剂材料，以及移除第一间隔物。

    INTEGRATED CIRCUIT STRUCTURE MANUFACTURING METHODS USING HARD MASK AND PHOTORESIST COMBINATION
    4.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE MANUFACTURING METHODS USING HARD MASK AND PHOTORESIST COMBINATION 审中-公开
    使用硬掩模和光电组合的集成电路结构制造方法

    公开(公告)号：US20100330756A1

    公开(公告)日：2010-12-30

    申请号：US12491270

    申请日：2009-06-25

    申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes

    发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/823807

    摘要： A method of manufacturing an integrated circuit structure implants a first-type of channel implant in a first area of a substrate and implants a second-type of channel implant in a second area of the substrate. The method forms at least one first gate conductor above the first area of the substrate and forms at least one second gate conductor above the second area of the substrate. The method forms a hard mask over the first gate conductor, the second gate conductor, and the substrate. The hard mask comprises an oxide or a nitride and patterns an organic photoresist over the hard mask, to leave the organic photoresist on areas of the hard mask that are above the first area of the substrate. The method removes portions of the hard mask not protected by the organic photoresist to leave the hard mask on the first area of the substrate and not on the second area of the substrate. The method then removes the organic photoresist, implants impurities in the second area of the substrate to form source and drain regions adjacent the second gate conductor; and removes the hard mask using a wet etching process.

    摘要翻译： 一种制造集成电路结构的方法是将衬底的第一区域中的第一种沟道注入植入，并在衬底的第二区域中注入第二类沟道注入。 该方法在衬底的第一区域之上形成至少一个第一栅极导体，并在衬底的第二区域上方形成至少一个第二栅极导体。 该方法在第一栅极导体，第二栅极导体和衬底上形成硬掩模。 硬掩模包括氧化物或氮化物，并且在硬掩模上形成有机光致抗蚀剂，以将有机光致抗蚀剂留在位于衬底的第一区域上方的硬掩模的区域上。 该方法除去未被有机光致抗蚀剂保护的硬掩模的部分，以将硬掩模留在衬底的第一区域上，而不在衬底的第二区域上。 该方法然后去除有机光致抗蚀剂，在衬底的第二区域内植入杂质以形成邻近第二栅极导体的源区和漏区; 并使用湿蚀刻工艺去除硬掩模。

    CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER
    6.
    发明申请
    CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER 审中-公开
    使用形成介质层的真实层形成的导电元件

    公开(公告)号：US20090032491A1

    公开(公告)日：2009-02-05

    申请号：US11833301

    申请日：2007-08-03

    申请人： Veeraraghavan S. Basker ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian

    发明人： Veeraraghavan S. Basker ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian

    IPC分类号： H01B13/00 ,  B32B3/10

    CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L2221/1026 ,  H01L2221/1031 ,  Y10T428/24273

    摘要： Methods of forming a conductive element for an integrated circuit (IC) chip and a related structure are disclosed. One embodiment of the method may include forming a first sacrificial layer having a pattern therein for a first dielectric layer to surround the conductive element; forming the first dielectric layer within the patterned first sacrificial layer; removing the patterned first sacrificial layer, leaving the first dielectric layer; and forming the conductive element in a space vacated by the patterned first sacrificial layer. The methods prevent damage caused to low dielectric constant dielectric layers during etching and stripping/cleaning processes.

    摘要翻译： 公开了形成用于集成电路（IC）芯片的导电元件和相关结构的方法。 该方法的一个实施例可以包括形成其中具有图案的第一牺牲层用于第一介电层以围绕导电元件; 在所述图案化的第一牺牲层内形成所述第一介电层; 去除图案化的第一牺牲层，留下第一介电层; 以及在由图案化的第一牺牲层腾出的空间中形成导电元件。 该方法防止在蚀刻和剥离/清洗过程中对低介电常数电介质层造成的损坏。

    MULTI-EXPOSURE LITHOGRAPHY EMPLOYING A SINGLE ANTI-REFLECTIVE COATING LAYER
    7.
    发明申请
    MULTI-EXPOSURE LITHOGRAPHY EMPLOYING A SINGLE ANTI-REFLECTIVE COATING LAYER 失效
    采用单反反射涂层的多次曝光光刻

    公开(公告)号：US20100009131A1

    公开(公告)日：2010-01-14

    申请号：US12169888

    申请日：2008-07-09

    申请人： Veeraraghavan S. Basker ,  Willard E. Conley ,  Steven J. Holmes ,  David V. Horak

    发明人： Veeraraghavan S. Basker ,  Willard E. Conley ,  Steven J. Holmes ,  David V. Horak

    IPC分类号： G03F7/20 ,  B32B9/00

    CPC分类号： G03F7/20 ,  G03F7/70466 ,  G03F7/70958 ,  H01L21/76816 ,  H01L21/76838 ,  Y10T428/24802

    摘要： A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.

    摘要翻译： 将第一光致抗蚀剂施加在光致密层上并且被光刻图案化以形成具有接近两倍最小特征尺寸的间距的第一光致抗蚀剂部分的阵列。 第一光致抗蚀剂部分或第一图案中的图案被转移到ARC层中并部分地转移到光致密层中。 施加第二光致抗蚀剂并将其图案化成具有接近最小特​​征尺寸的两倍的间距的另一阵列并与第一图案隔行扫描。 第二光致抗蚀剂或第二图案中的图案通过ARC部分转移并部分地转移到光致密层中。 ARC部分用包括第一图案和第二图案的复合图案图案化。 复合图案通过光致密层转移到底层中以在底层中形成亚光刻图案。

    ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD
    8.
    发明申请
    ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD 有权
    抗保护器件结构和电镀电路结构与方法

    公开(公告)号：US20090206447A1

    公开(公告)日：2009-08-20

    申请号：US12031761

    申请日：2008-02-15

    申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    IPC分类号： H01L23/525 ,  H01L21/44

    CPC分类号： H01L23/5252 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

    摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

    Multi-exposure lithography employing a single anti-reflective coating layer
    9.
    发明授权
    Multi-exposure lithography employing a single anti-reflective coating layer 失效
    使用单个抗反射涂层的多曝光光刻

    公开(公告)号：US08507187B2

    公开(公告)日：2013-08-13

    申请号：US12169888

    申请日：2008-07-09

    申请人： Veeraraghavan S. Basker ,  Willard E. Conley ,  Steven J. Holmes ,  David V. Horak

    发明人： Veeraraghavan S. Basker ,  Willard E. Conley ,  Steven J. Holmes ,  David V. Horak

    IPC分类号： G03F7/20

    CPC分类号： G03F7/20 ,  G03F7/70466 ,  G03F7/70958 ,  H01L21/76816 ,  H01L21/76838 ,  Y10T428/24802

    摘要： A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.

    摘要翻译： 将第一光致抗蚀剂施加在光致密层上并且被光刻图案化以形成具有接近两倍最小特征尺寸的间距的第一光致抗蚀剂部分的阵列。 第一光致抗蚀剂部分或第一图案中的图案被转移到ARC层中并部分地转移到光致密层中。 施加第二光致抗蚀剂并将其图案化成具有接近最小特​​征尺寸的两倍的间距的另一阵列并与第一图案隔行扫描。 第二光致抗蚀剂或第二图案中的图案通过ARC部分转移并部分地转移到光致密层中。 ARC部分用包括第一图案和第二图案的复合图案图案化。 复合图案通过光致密层转移到底层中以在底层中形成亚光刻图案。

    ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD
    10.
    发明申请
    ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD 有权
    抗保护器件结构和电镀电路结构与方法

    公开(公告)号：US20120261795A1

    公开(公告)日：2012-10-18

    申请号：US13535393

    申请日：2012-06-28

    申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5252 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

    摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。