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公开(公告)号：US20210175418A1
公开(公告)日：2021-06-10
申请号：US16709863
申请日：2019-12-10
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
IPC: H01L45/00
Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.
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公开(公告)号：US10916307B2
公开(公告)日：2021-02-09
申请号：US16726206
申请日：2019-12-23
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Ping-Kun Wang
Abstract: A resistive memory apparatus and an operating method thereof are provided. In the method, a set operation having a first enhanced bias is performed on at least one memory cell in a resistive memory array of the resistive memory apparatus, in which the first enhanced bias is larger than a bias used in a normal execution of the set operation. A heat process is performed on the memory cell. A set operation having a second enhanced bias is performed on the memory cell, in which the second enhanced bias is larger than or equal to the first enhanced bias.
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公开(公告)号：US10658036B2
公开(公告)日：2020-05-19
申请号：US16045749
申请日：2018-07-26
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Ping-Kun Wang , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.
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公开(公告)号：US10475513B2
公开(公告)日：2019-11-12
申请号：US15997717
申请日：2018-06-05
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Ming-Che Lin , Min-Chih Wei , Chuan-Sheng Chou
Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.
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公开(公告)号：US20160351623A1
公开(公告)日：2016-12-01
申请号：US14726626
申请日：2015-06-01
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao
CPC classification number: H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/04 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/1273 , H01L45/146 , H01L45/147
Abstract: A resistive random access memory is provided. The resistive memory cell includes a substrate, a transistor on the substrate, a bottom electrode on the substrate and electrically connected to the transistor source/drain, several top electrodes on the bottom electrode, several resistance-switching layers between the top and bottom electrode, and several current limiting layers between the resistance-switching layer and top electrodes. The cell could improve the difficulty on recognizing 1/0 signal by current at high temperature environment and save the area on the substrate by generating several conductive filaments at one transistor location.
Abstract translation: 提供了一种电阻式随机存取存储器。 电阻式存储单元包括衬底，衬底上的晶体管，衬底上的底部电极，并电连接到晶体管源极/漏极，底部电极上的几个顶部电极，顶部和底部电极之间的几个电阻切换层， 以及电阻切换层和顶部电极之间的若干电流限制层。 该电池可以提高在高温环境下通过电流识别1/0信号的难度，并通过在一个晶体管位置产生几个导电细丝来节省基板上的面积。
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Patent Agency Ranking
公开(公告)号：US20160315255A1
公开(公告)日：2016-10-27
申请号：US15067184
申请日：2016-03-11
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Meng-Hung Lin
IPC: H01L45/00
CPC classification number: H01L45/1266 , H01L45/08 , H01L45/1233 , H01L45/146
Abstract: A resistive random access memory (RRAM) including a first electrode, a second electrode, and a variable-resistance oxide layer disposed between the first electrode and the second electrode is provided. The RRAM further includes an oxygen exchange layer, an oxygen-rich layer, and a first oxygen barrier layer. The oxygen exchange layer is disposed between the variable-resistance oxide layer and the second electrode. The oxygen-rich layer is disposed between the oxygen exchange layer and the second electrode. The first oxygen barrier layer is disposed between the oxygen exchange layer and the oxygen-rich layer.
Abstract translation: 提供了包括设置在第一电极和第二电极之间的第一电极，第二电极和可变电阻氧化物层的电阻随机存取存储器（RRAM）。 RRAM还包括氧交换层，富氧层和第一氧阻隔层。 氧交换层设置在可变电阻氧化物层和第二电极之间。 富氧层设置在氧交换层和第二电极之间。 第一氧阻隔层设置在氧交换层和富氧层之间。
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公开(公告)号：US11176996B2
公开(公告)日：2021-11-16
申请号：US15930469
申请日：2020-05-13
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.
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公开(公告)号：US20190035459A1
公开(公告)日：2019-01-31
申请号：US16045749
申请日：2018-07-26
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Ping-Kun Wang , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.
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公开(公告)号：US20190006007A1
公开(公告)日：2019-01-03
申请号：US15729676
申请日：2017-10-11
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
IPC: G11C13/00
Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.
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公开(公告)号：US10170184B1
公开(公告)日：2019-01-01
申请号：US15729676
申请日：2017-10-11
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Ming-Che Lin , Min-Chih Wei , Chia-Hua Ho , Chien-Min Wu
IPC: G11C13/00
Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.
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