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    CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED CIRCUIT
    21.
    发明申请
    CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED CIRCUIT 有权
    在集成电路中控制电源的电路和方法

    公开(公告)号：US20160118988A1

    公开(公告)日：2016-04-28

    申请号：US14526192

    申请日：2014-10-28

    Applicant: Xilinx, Inc.

    Inventor： Santosh Kumar Sood ,  Brian C. Gaide ,  Steven P. Young

    IPC: H03K19/177 ,  H03K19/00

    CPC classification number: H03K19/17784 ,  H03K19/0008 ,  H03K19/0016

    Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

    Abstract translation: 用于控制集成电路内的电力的电路包括多个电路块; 在集成电路内布线的全局控制信号; 和多个功率控制块。 每个功率控制块耦合到多个电路块的相应电路块，并且具有耦合以接收参考电压的第一输入和耦合以接收全局控制信号的第二输入。 对于每个电路块，全局控制信号使得参考电压与对应的电路块的耦合。 还公开了一种控制集成电路内的功率的方法。

    Circuits for and methods of asychronously transmitting data in an integrated circuit
    23.
    发明授权
    Circuits for and methods of asychronously transmitting data in an integrated circuit 有权
    用于在集成电路中异步传输数据的电路和方法

    公开(公告)号：US08928386B1

    公开(公告)日：2015-01-06

    申请号：US13797791

    申请日：2013-03-12

    Applicant: Xilinx, Inc.

    Inventor： Ilya Ganusov ,  Brian C. Gaide

    IPC: H03K3/00 ,  H03K5/13 ,  G06F13/40 ,  H04L1/00

    CPC classification number: H03K5/13 ,  G06F13/4009 ,  H03K19/00315 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0052

    Abstract: A circuit for asynchronously transmitting data in an integrated circuit is described. The circuit comprises a transmitter circuit generating data to be transmitted at an output; a first register having an input, an output and a clock input, wherein the input of the first register is coupled to the output of the transmitter and the clock input of the first register is coupled to receive a clock signal; at least one asynchronous buffer having an input and an output, wherein the input is coupled to the output of the first register; a receiver circuit coupled to the output of the at least one buffer; and a second register having an input, and output and a clock input, wherein the input of the at least one asynchronous buffer is coupled to the output of the transmitter and the clock input of the second register is coupled to receive the clock signal. A method of implementing of asynchronously transmitting data in an integrated circuit device is also disclosed.

    Abstract translation: 描述用于在集成电路中异步传输数据的电路。 该电路包括发送器电路，产生要在输出端发送的数据; 具有输入，输出和时钟输入的第一寄存器，其中所述第一寄存器的输入耦合到所述发送器的输出，并且所述第一寄存器的时钟输入被耦合以接收时钟信号; 至少一个具有输入和输出的异步缓冲器，其中所述输入耦合到所述第一寄存器的输出; 耦合到所述至少一个缓冲器的输出的接收器电路; 以及具有输入和输出以及时钟输入的第二寄存器，其中所述至少一个异步缓冲器的输入耦合到所述发送器的输出，并且所述第二寄存器的时钟输入被耦合以接收所述时钟信号。 还公开了一种在集成电路器件中实现异步发送数据的方法。

    Power delivery network for active-on-active stacked integrated circuits
    27.
    发明授权
    Power delivery network for active-on-active stacked integrated circuits 有权

    公开(公告)号：US11270977B2

    公开(公告)日：2022-03-08

    申请号：US16679063

    申请日：2019-11-08

    Applicant: XILINX, INC.

    Inventor： Praful Jain ,  Steven P. Young ,  Martin L. Voogel ,  Brian C. Gaide

    IPC: H01L25/065 ,  H01L25/00

    Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.

    Programmable termination circuits for programmable devices
    28.
    发明授权
    Programmable termination circuits for programmable devices 有权

    公开(公告)号：US10998904B1

    公开(公告)日：2021-05-04

    申请号：US16686073

    申请日：2019-11-15

    Applicant: Xilinx, Inc.

    Inventor： Sundeep Ram Gopal Agarwal ,  Brian C. Gaide ,  Ramakrishna Kishore Tanikella

    IPC: H03K19/00 ,  H01L25/065

    Abstract: Configurable termination circuits for use with programmable logic devices are disclosed. In one implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to a fixed voltage. In another implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to an output of the one or more configurable logic blocks. In some implementations, the programmable logic device may include a platform management controller to configure the termination circuits based on configuration data.

    REDUNDANCY SCHEME FOR A 3D STACKED DEVICE
    30.
    发明申请
    REDUNDANCY SCHEME FOR A 3D STACKED DEVICE 审中-公开

    公开(公告)号：US20190333892A1

    公开(公告)日：2019-10-31

    申请号：US15967109

    申请日：2018-04-30

    Applicant: Xilinx, Inc.

    Inventor： Brian C. Gaide ,  Matthew H. Klein

    IPC: H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/535

    Abstract: Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

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