公开(公告)号：US6154411A

公开(公告)日：2000-11-28

申请号：US324802

申请日：1999-06-03

申请人： Fukashi Morishita

发明人： Fukashi Morishita

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  H02M3/07 ,  G11C7/00

CPC分类号： G11C5/145 ,  G11C11/4074

摘要： A boosting circuit is provided with a voltage detection circuit, first through fourth oscillators, and first through fourth charge pump circuits. The voltage detection circuit compares each of the first through fourth voltages obtained by dividing a boosted voltage with a reference voltage, and generates first through fourth activation signals. The first through fourth oscillators output pulse signals at first through fourth frequencies, respectively, as first through fourth drive signals. The first through fourth charge pump circuits operate in response to the first through fourth drive signals, respectively, and boost the boosted voltage. Accordingly, it is possible to provide a stable boosted voltage, with suppressing over shoot and under shoot with respect to the boosted voltage as a target.

摘要翻译： 升压电路具有电压检测电路，第一至第四振荡器以及第一至第四电荷泵电路。 电压检测电路将通过将升压电压分压获得的第一至第四电压与参考电压进行比较，并且产生第一至第四激活信号。 第一至第四振荡器分别以第一至第四驱动信号在第一至第四频率处输出脉冲信号。 第一至第四电荷泵电路分别响应于第一至第四驱动信号而工作，并升压升压电压。 因此，可以提供稳定的升压电压，相对于作为目标的升压电压抑制过拍和下拍。

公开(公告)号：US5909046A

公开(公告)日：1999-06-01

申请号：US965618

申请日：1997-11-06

申请人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0248 ,  H01L24/05 ,  H01L2924/14

摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.

摘要翻译： 导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。 具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。 由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏 可以获得耐热性，并且可以获得耐喘振性的改善。

公开(公告)号：US08466718B2

公开(公告)日：2013-06-18

申请号：US13081957

申请日：2011-04-07

申请人： Yoshiyuki Ezumi ,  Fukashi Morishita

发明人： Yoshiyuki Ezumi ,  Fukashi Morishita

IPC分类号： H03K3/00

CPC分类号： H03K19/00361 ,  H03K19/018528

摘要： Disclosed is a semiconductor device having an output driver and a driver replica. The output driver is based on a scalable low-voltage signaling technology and capable of operating on low power and making automatic adjustments of output characteristics in accordance with the magnitude of a reference current. The driver replica, which is a duplicate of the output driver, adjusts the magnitude of the reference current in accordance with the difference between its own output and a reference voltage and outputs the adjusted current to the output driver.

摘要翻译： 公开了具有输出驱动器和驱动器副本的半导体器件。 输出驱动器基于可扩展的低电压信号技术，能够以低功耗运行，并根据参考电流的大小自动调整输出特性。 与输出驱动器重复的驱动器副本根据其自身的输出和参考电压之间的差异来调整参考电流的大小，并将调整的电流输出到输出驱动器。

公开(公告)号：US08451678B2

公开(公告)日：2013-05-28

申请号：US13080114

申请日：2011-04-05

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US08188534B2

公开(公告)日：2012-05-29

申请号：US13022864

申请日：2011-02-08

申请人： Fukashi Morishita ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Kazutami Arimoto

IPC分类号： H01L29/788 ,  H01L27/01 ,  H01L27/12

CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

公开(公告)号：US20120112039A1

公开(公告)日：2012-05-10

申请号：US13277921

申请日：2011-10-20

申请人： Hiroki Sugano ,  Fukashi Morishita

发明人： Hiroki Sugano ,  Fukashi Morishita

IPC分类号： H01L27/146

CPC分类号： H04N5/3532 ,  H04N5/3745 ,  H04N5/376

摘要： An image sensor with a small circuit area is provided. In the image sensor, a TX decoder which generates transfer signals TX includes a latch circuit. The latch circuit is set when a corresponding row group is selected and when a set signal is set to an “H” level, and is reset when a reset signal is set to an “L” level. The latch circuit serves also as a voltage level shift circuit which converts the “H” level of a signal from a first power supply voltage into a second power supply voltage. Therefore, plural row groups can be selected by setting plural latch circuits. It is not necessary to provide a voltage level shift circuit separately.

摘要翻译： 提供具有小电路面积的图像传感器。 在图像传感器中，产生传送信号TX <3：0>的TX解码器包括锁存电路。 当选择相应的行组并且将设置信号设置为“H”电平时，锁存电路被设置，并且当复位信号被设置为“L”电平时，锁存电路被复位。 锁存电路还用作电压电平移位电路，其将来自第一电源电压的信号的“H”电平转换为第二电源电压。 因此，可以通过设置多个锁存电路来选择多个行组。 不需要单独提供电压电平移位电路。

公开(公告)号：US07652927B2

公开(公告)日：2010-01-26

申请号：US11797804

申请日：2007-05-08

申请人： Fukashi Morishita ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Kazutami Arimoto

IPC分类号： G11C16/06

CPC分类号： G11C7/14 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/7841

摘要： When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).

摘要翻译： 当数据“1”被存储在存储单元中时，当感测操作完成时，位线被驱动到H电平（控制线驱动电位），另一个位线被驱动到L电平（参考电位）。 当启动验证写操作时，充电线从H电平（电源电位）驱动到L电平（参考电位）。 通过来自源极线的GIDL电流，在空穴放电之后对于存储节点再次开始空穴累积，由此存储节点的电位向上升到H电平（周期α）。 当充电线从L电平驱动到H电平时，存储节点的电位进一步上升（周期β）。

公开(公告)号：US07479820B2

公开(公告)日：2009-01-20

申请号：US11272798

申请日：2005-11-15

申请人： Mako Okamoto ,  Fukashi Morishita

发明人： Mako Okamoto ,  Fukashi Morishita

IPC分类号： G05F3/02

CPC分类号： G11C5/145 ,  G11C11/4074 ,  G11C11/4085 ,  H03K5/2481

摘要： A detector circuit and a negative voltage generating circuit capable of performing high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors and make the voltage division between the negative voltage and the power supply to obtain the detect potential.

摘要翻译： 提供能够执行高速操作的检测器电路和负电压产生电路。 负电压产生电路包括电荷泵电路，在电荷泵电路的输出和电源之间进行分压以输出检测电位的第一分压电路，产生参考电位的基准电压产生电路， 以及比较电路，其比较检测电位和参考电位。 电荷泵电路由比较器电路的输出信号驱动，并产生负电压。 在第一分压电路中，NMOS晶体管和负电压和电源之间的分压获得检测电位。

公开(公告)号：US20080298156A1

公开(公告)日：2008-12-04

申请号：US12170055

申请日：2008-07-09

申请人： Kenji YOSHINAGA ,  Masashi Matsumura ,  Futoshi Igaue ,  Mihoko Akiyama ,  Fukashi Morishita

发明人： Kenji YOSHINAGA ,  Masashi Matsumura ,  Futoshi Igaue ,  Mihoko Akiyama ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G11C29/48 ,  G11C29/12 ,  G11C29/12005

摘要： A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.

摘要翻译： 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。

公开(公告)号：US20080137394A1

公开(公告)日：2008-06-12

申请号：US12000343

申请日：2007-12-12

申请人： Hiroki Shimano ,  Fukashi Morishita ,  Kazutami Arimoto

发明人： Hiroki Shimano ,  Fukashi Morishita ,  Kazutami Arimoto

IPC分类号： G11C5/06

CPC分类号： G11C8/16 ,  G11C5/063 ,  G11C7/12 ,  G11C7/18 ,  G11C11/405 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.

摘要翻译： 一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。 第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。 当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。 可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。