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公开(公告)号：US20080137394A1
公开(公告)日：2008-06-12
申请号：US12000343
申请日：2007-12-12
IPC分类号： G11C5/06
CPC分类号： G11C8/16 , G11C5/063 , G11C7/12 , G11C7/18 , G11C11/405 , G11C11/4094 , G11C11/4097 , G11C2211/4016 , H01L21/84 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.
摘要翻译： 一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。 第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。 当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。 可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。
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公开(公告)号：US07738312B2
公开(公告)日：2010-06-15
申请号：US12000343
申请日：2007-12-12
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/12 , G11C7/18 , G11C11/405 , G11C11/4094 , G11C11/4097 , G11C2211/4016 , H01L21/84 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.
摘要翻译： 一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。 第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。 当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。 可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。
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公开(公告)号：US07910975B2
公开(公告)日：2011-03-22
申请号：US10593275
申请日：2005-06-03
IPC分类号： H01L29/788 , H01L27/01 , H01L27/12
CPC分类号： G11C11/405 , G11C2211/4016 , H01L27/108 , H01L27/10802
摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.
摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。
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公开(公告)号：US06272034B1
公开(公告)日：2001-08-07
申请号：US09606402
申请日：2000-06-29
申请人： Mitsuya Kinoshita , Fukashi Morishita , Kazutami Arimoto , Takeshi Fujino , Tetsushi Tanizaki , Takahiro Tsuruda , Teruhiko Amano , Mako Kobayashi
发明人： Mitsuya Kinoshita , Fukashi Morishita , Kazutami Arimoto , Takeshi Fujino , Tetsushi Tanizaki , Takahiro Tsuruda , Teruhiko Amano , Mako Kobayashi
IPC分类号： G11C502
CPC分类号： G11C5/025
摘要： A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.
摘要翻译： 控制存储器单元的操作的控制电路部分集中在中心部分，并且热辐射板通过粘合剂放置在其上。 具有MPU等的功能的半导体集成电路经由凸块电极放置在控制电路部分上方。 控制电路部分和存储块分别形成在分开的芯片上。
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5.发明授权Semiconductor integrated circuit device having stable input protection circuit 失效半导体集成电路器件具有稳定的输入保护电路
公开(公告)号：US5909046A
公开(公告)日：1999-06-01
申请号：US965618
申请日：1997-11-06
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L23/62
CPC分类号： H01L27/0248 , H01L24/05 , H01L2924/14
摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.
摘要翻译： 导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。 具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。 由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏 可以获得耐热性，并且可以获得耐喘振性的改善。
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公开(公告)号：US08188534B2
公开(公告)日：2012-05-29
申请号：US13022864
申请日：2011-02-08
IPC分类号： H01L29/788 , H01L27/01 , H01L27/12
CPC分类号： G11C11/405 , G11C2211/4016 , H01L27/108 , H01L27/10802
摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.
摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。
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公开(公告)号：US07652927B2
公开(公告)日：2010-01-26
申请号：US11797804
申请日：2007-05-08
IPC分类号： G11C16/06
CPC分类号： G11C7/14 , G11C7/065 , G11C7/08 , G11C7/1048 , G11C11/405 , G11C11/4091 , G11C11/4099 , G11C2207/002 , G11C2207/005 , G11C2207/2281 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/10897 , H01L27/1203 , H01L29/7841
摘要： When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).
摘要翻译： 当数据“1”被存储在存储单元中时，当感测操作完成时，位线被驱动到H电平（控制线驱动电位），另一个位线被驱动到L电平（参考电位）。 当启动验证写操作时，充电线从H电平（电源电位）驱动到L电平（参考电位）。 通过来自源极线的GIDL电流，在空穴放电之后对于存储节点再次开始空穴累积，由此存储节点的电位向上升到H电平（周期α）。 当充电线从L电平驱动到H电平时，存储节点的电位进一步上升（周期β）。
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8.发明授权Semiconductor memory device capable of increasing chip yields while maintaining rapid operation 失效半导体存储器件能够在保持快速操作的同时提高芯片产量
公开(公告)号：US5914907A
公开(公告)日：1999-06-22
申请号：US122760
申请日：1998-07-27
申请人： Mako Kobayashi , Tetsushi Tanizaki , Kazutami Arimoto , Teruhiko Amano , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Mitsuya Kinoshita
发明人： Mako Kobayashi , Tetsushi Tanizaki , Kazutami Arimoto , Teruhiko Amano , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Mitsuya Kinoshita
摘要： Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.
摘要翻译： 常规存储单元阵列被布置在除了位于第二行和第二列的区域之外的三行和三列的分割区域中。 位于第二行和第二列的交叉点的区域设置有冗余存储单元阵列。 为每个存储单元块提供具有冗余存储单元阵列的常规存储单元阵列的替换操作。
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公开(公告)号：US07764540B2
公开(公告)日：2010-07-27
申请号：US12281271
申请日：2006-03-01
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON.
摘要翻译： 通过与设置为OFF的存储晶体管并行地激活字线和位线，控制充电线，字线和位线的电位条件，使得身体区域的电位增加一 在存储晶体管导通的期间内，从连接节点流向身体区域的漏电流。
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公开(公告)号：US20070263466A1
公开(公告)日：2007-11-15
申请号：US11797804
申请日：2007-05-08
IPC分类号： G11C7/02
CPC分类号： G11C7/14 , G11C7/065 , G11C7/08 , G11C7/1048 , G11C11/405 , G11C11/4091 , G11C11/4099 , G11C2207/002 , G11C2207/005 , G11C2207/2281 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/10897 , H01L27/1203 , H01L29/7841
摘要： When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).
摘要翻译： 当数据“1”被存储在存储单元中时，当感测操作完成时，位线被驱动到H电平（控制线驱动电位），另一个位线被驱动到L电平（参考电位）。 当启动验证写操作时，充电线从H电平（电源电位）驱动到L电平（参考电位）。 通过来自源极线的GIDL电流，在空穴放电之后对于存储节点再次开始空穴累积，由此存储节点的电位向上升到H电平（周期α）。 当充电线从L电平驱动到H电平时，存储节点的电位进一步上升（周期β）。
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