公开(公告)号：US08643135B2

公开(公告)日：2014-02-04

申请号：US13134163

申请日：2011-05-31

申请人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

发明人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

IPC分类号： H01L23/58 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/407 ,  H01L29/0661 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

摘要翻译： 本发明公开了一种半导体功率器件，其设置在半导体衬底中并且具有有源电池区域和边缘终止区域，其中边缘终端区域包括填充有场强拥挤减少填充物的宽沟槽和埋在顶表面下方的掩埋场板 并且横向延伸超过场域拥挤场的顶部以使峰值电场横向移动到有源电池区域。 在一个具体的实施例中，场地拥挤减少填料包括填充在宽沟槽中的氧化硅。

公开(公告)号：US20130277740A1

公开(公告)日：2013-10-24

申请号：US13923065

申请日：2013-06-20

申请人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

发明人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

IPC分类号： H01L29/78

CPC分类号： H01L29/7823 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/47 ,  H01L29/7811

摘要： A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions.

摘要翻译： 公开了一种用于布置设计和超级结装置制造的超结装置和方法。 可以配置活性单元列结构的布局，使得由于第一导电型掺杂剂引起的电荷由于活性单元区域中的掺杂层中的第二导电类型掺杂物而平衡电荷。 靠近端子列结构的活性单元列结构的端部的布局可以被配置为使得由于端部中的第一导电类型掺杂物引起的电荷和由端接塔结构中的第一导电类型掺杂剂引起的电荷平衡 在终端柱结构和端部之间的掺杂层的一部分中的第二导电类型掺杂剂引起的电荷。

公开(公告)号：US20130260522A1

公开(公告)日：2013-10-03

申请号：US13900162

申请日：2013-05-22

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7802 ,  H01L29/7811

摘要： A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

摘要翻译： 交错列超结半导体器件可以包括具有一个或多个器件单元的单元区域。 单元区域中的一个或多个器件单元包括被配置为用作漏极的半导体衬底和形成在衬底上的半导体层。 第一掺杂柱可以在半导体层中形成为第一深度，并且第二掺杂柱可以形成在半导体层中至第二深度。 第一个深度大于第二个深度。 第一和第二列掺杂有相同第二导电类型的掺杂剂并且沿着半导体层的厚度的一部分延伸并且由半导体层的一部分分离。

公开(公告)号：US20130049102A1

公开(公告)日：2013-02-28

申请号：US13199381

申请日：2011-08-25

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Lingpeng Guan ,  Jun Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate comprises a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region. The semiconductor power device further comprises a body region, a source region and a gate disposed near the top surface of the semiconductor substrate and a drain disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises a buried field ring regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. In an alternate embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried field ring regions to function as a charge supply path.

摘要翻译： 本发明公开了一种形成在半导体衬底中的半导体功率器件，包括在轻掺杂区域顶部附近的半导体衬底的顶表面附近的高掺杂区域。 半导体功率器件还包括设置在半导体衬底的顶表面附近的体区，源区和栅极以及设置在半导体衬底的底表面处的漏极。 半导体功率器件还包括开口到高掺杂区域的源沟槽，填充有与顶表面附近的源区电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域具有相反导电性的掺杂剂的掩埋场环区域。 在替代实施例中，半导体功率器件还包括围绕源极沟槽的侧壁的掺杂区域，并掺杂有相同导电类型的掩埋场环区域的掺杂剂，用作电荷供应路径。

公开(公告)号：US08373208B2

公开(公告)日：2013-02-12

申请号：US12799810

申请日：2010-04-30

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L21/8232

CPC分类号： H01L29/808 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66696 ,  H01L29/66901 ,  H01L29/7817 ,  H01L29/7821

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

摘要翻译： 横向超结JFET由负载在N +衬底上的P表面层上的堆叠的交替P型和N型半导体层形成。 N +漏极柱向下延伸穿过超结结构和P-epi以连接到N +衬底以使器件成为底部漏极器件。 N +源极柱和P +栅极柱延伸穿过超级结，但在P-epi层处停止。 栅极 - 漏极雪崩钳位二极管从P +栅极底部通过P-epi到N +漏极衬底形成。

公开(公告)号：US20130001694A1

公开(公告)日：2013-01-03

申请号：US13170965

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC分类号： H01L23/60 ,  H01L21/336

CPC分类号： H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

摘要： A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

摘要翻译： 具有降低的钳位电压的低电容瞬态电压抑制器包括n +型衬底，衬底上的第一外延层，形成在第一外延层内的掩埋层，在第一外延层上形成的第二外延层，以及在第一外延层上形成的注入层 掩埋层下面的第一个外延层。 植入层延伸超过掩埋层。 第一沟槽位于掩埋层的边缘和植入层的边缘。 第二沟槽位于掩埋层的另一边缘并延伸到植入层中。 第三沟槽位于植入层的另一边缘。 每个沟槽衬有介电层。 一组源区形成在第二外延层的顶表面内。 沟渠和源区交替出现。 在第二外延层中形成一对注入区。

公开(公告)号：US20120319132A1

公开(公告)日：2012-12-20

申请号：US13162407

申请日：2011-06-16

申请人： Anup Bhalla ,  Madhur Bobde ,  Lingpeng Guan

发明人： Anup Bhalla ,  Madhur Bobde ,  Lingpeng Guan

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/47 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7806

摘要： An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region.

摘要翻译： 集成结构包括多个分离栅沟槽MOSFET。 在碳化硅衬底组合物中形成多个沟槽，每个沟槽衬有钝化层，每个沟槽基本上填充有第一导电区域，第二导电区域和绝缘材料，其介电常数类似于介电常数 碳化硅衬底组合物。 第一导电区域通过绝缘材料与钝化层分离。 第一和第二导电区域形成每个沟槽MOSFET的栅极区域。 第一导电区域通过钝化层与第二导电区域分离。 在衬底组合物的上部形成的第一导电类型的掺杂体区域和形成在掺杂体区域内的第二导电类型的掺杂源区。

公开(公告)号：US20120104555A1

公开(公告)日：2012-05-03

申请号：US12925869

申请日：2010-10-31

申请人： Madhur Bobde ,  Anup Bhalla

发明人： Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66348

摘要： This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

摘要翻译： 本发明公开了一种形成在半导体衬底中的绝缘栅双极晶体管（IGBT）器件。 IGBT器件具有分裂屏蔽沟槽栅极，其包括上栅极段和下屏蔽段。 IGBT器件还可以包括填充有离开分屏蔽沟槽栅极一定距离设置的电介质层的虚拟沟槽。 IGBT器件还包括在分屏蔽沟槽栅极和虚拟沟槽之间延伸的体区，其围绕半导体衬底的顶表面附近的分离屏蔽沟槽栅极的源极区域。 所述IGBT器件还包括设置在所述体区域的下方且位于所述半导体衬底的底表面的底体 - 掺杂剂集电极区域上方的源 - 掺杂剂漂移区上方的重掺杂N区域。 在替代实施例中，IGBT可以包括具有沟槽屏蔽电极的平面栅极。

公开(公告)号：US20100276779A1

公开(公告)日：2010-11-04

申请号：US12433358

申请日：2009-04-30

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/34 ,  H01L21/265 ,  H01L21/76 ,  H01L21/20

CPC分类号： H01L29/861 ,  H01L27/0259 ,  H01L29/10 ,  H01L29/6609

摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

摘要翻译： 垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底被重掺杂;第一导电类型的外延层，形成在衬底上，外延层具有第一厚度;以及基极区 形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。 基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。 在一个实施例中，通过高能量注入形成基极区域。 在另一个实施例中，基底区形成为掩埋层。 选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。

公开(公告)号：US10103240B2

公开(公告)日：2018-10-16

申请号：US13763675

申请日：2013-02-10

申请人： Madhur Bobde ,  Lingpeng Guann ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guann ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.