公开(公告)号：US08643135B2

公开(公告)日：2014-02-04

申请号：US13134163

申请日：2011-05-31

申请人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

发明人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

IPC分类号： H01L23/58 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/407 ,  H01L29/0661 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

摘要翻译： 本发明公开了一种半导体功率器件，其设置在半导体衬底中并且具有有源电池区域和边缘终止区域，其中边缘终端区域包括填充有场强拥挤减少填充物的宽沟槽和埋在顶表面下方的掩埋场板 并且横向延伸超过场域拥挤场的顶部以使峰值电场横向移动到有源电池区域。 在一个具体的实施例中，场地拥挤减少填料包括填充在宽沟槽中的氧化硅。

公开(公告)号：US07737522B2

公开(公告)日：2010-06-15

申请号：US11541189

申请日：2006-09-30

申请人： Sik K Lui ,  Anup Bhalla

发明人： Sik K Lui ,  Anup Bhalla

IPC分类号： H01L29/47 ,  H01L29/872

CPC分类号： H01L29/66727 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/782 ,  H01L29/8725

摘要： A Schottky diode includes at least a trenched opened in a semiconductor substrate doped with a dopant of a first conductivity type wherein the trench is filled with a Schottky junction barrier metal. The Schottky diode further includes one or more dopant region of a second conductivity type surrounding sidewalls of the trench distributed along the depth of the trench for shielding a reverse leakage current through the sidewalls of the trench. The Schottky diode further includes a bottom-doped region of the second conductivity type surrounding a bottom surface of the trench and a top-doped region of the second conductivity type surrounding a top portion of the sidewalls of the trench. In a preferred embodiment, the first conductivity type is a N-type conductivity type and the middle-depth dopant region comprising a P-dopant region.

摘要翻译： 肖特基二极管包括在掺杂有第一导电类型的掺杂剂的半导体衬底中开放的至少沟槽，其中沟槽填充有肖特基结阻挡金属。 所述肖特基二极管还包括一个或多个第二导电类型的掺杂区，该沟道围绕所述沟槽的深度分布，用于屏蔽穿过沟槽的侧壁的反向漏电流。 肖特基二极管还包括围绕沟槽的底表面的第二导电类型的底部掺杂区域和围绕沟槽的侧壁的顶部的第二导电类型的顶部掺杂区域。 在优选实施例中，第一导电类型是N型导电类型，并且中间深度掺杂区包含P掺杂区域。

公开(公告)号：US07671662B2

公开(公告)日：2010-03-02

申请号：US12290270

申请日：2008-10-28

申请人： Sik K Lui ,  Anup Bhalla ,  Sanjay Havanur

发明人： Sik K Lui ,  Anup Bhalla ,  Sanjay Havanur

IPC分类号： H01L35/00

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/7803 ,  H01L29/7804 ,  H03K17/08122 ,  H03K2017/0806

摘要： A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.

摘要翻译： 半导体功率器件包括提供栅极信号的电路，其中栅极信号具有负温度系数的栅极驱动电压，用于随温度升高而降低栅极驱动电压，由此半导体功率器件的净Ids温度系数小于 或等于零。 在示例性实施例中，栅极电压驱动器包括具有连接在半导体功率器件的栅极和源极之间的正向正向电压温度系数的二极管。 在另一个实施例中，栅极电压与作为与半导体功率器件的集成电路的一部分制造的半导体功率器件集成。

公开(公告)号：US08008716B2

公开(公告)日：2011-08-30

申请号：US11522669

申请日：2006-09-17

申请人： Sik K Lui ,  François Hébert ,  Anup Bhalla

发明人： Sik K Lui ,  François Hébert ,  Anup Bhalla

IPC分类号： H01L29/66

CPC分类号： H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉降通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

公开(公告)号：US07355433B2

公开(公告)日：2008-04-08

申请号：US11300082

申请日：2005-12-14

申请人： Sik K Lui ,  Anup Bhalla

发明人： Sik K Lui ,  Anup Bhalla

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2621 ,  G01R31/2831 ,  G01R31/327

摘要： This invention discloses a circuit for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device driven by a gate driver. The circuit includes a current sense circuit for measuring an unclamped inductive testing (UIS) current that increases with an increase of a pulse width inputted from the gate driver to the MOSFET device wherein the current sensing circuit is provided to turn off the gate driver when a predefined UIS current is reached. The test circuit further includes a MOSFET failure detection circuit connected to a drain terminal of the MOSFET device for measuring a drain voltage change for detecting the MOSFET failure during the UIS test. The test circuit further includes a first switch for switching ON/OFF a power supply to the MOSFET device to and a second switch connected between a drain and source terminal of the MOSFET. Furthermore, the test circuit further includes a timing and make before break (MBB) circuit for receiving an MOSFET failure signal from the MOSFET failure detection circuit and for controlling the first and second switches for switching off a power supply to the MOSFET device upon a detection of an UIS failure under the UIS test to prevent damages to a probe

摘要翻译： 本发明公开了一种用于对由栅极驱动器驱动的金属氧化物半导体场效应晶体管（MOSFET）器件执行未钳位电感测试的电路。 该电路包括电流检测电路，用于测量从栅极驱动器输入到MOSFET器件的脉冲宽度增加而增加的未钳位电感测试（UIS）电流，其中提供电流检测电路以在栅极驱动器 达到预定义的UIS电流。 测试电路还包括连接到MOSFET器件的漏极端子的MOSFET故障检测电路，用于测量在UIS测试期间检测MOSFET故障的漏极电压变化。 测试电路还包括用于将MOSFET器件的电源接通/断开的第一开关和连接在MOSFET的漏极和源极端子之间的第二开关。 此外，测试电路还包括用于从MOSFET故障检测电路接收MOSFET故障信号的定时和断开前（MBB）电路，并且用于在检测时控制用于关断到MOSFET器件的电源的第一和第二开关 在统计研究所测试下的统计研究所失败，以防止探针受损

公开(公告)号：US09024378B2

公开(公告)日：2015-05-05

申请号：US13763644

申请日：2013-02-09

申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K Lui

发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K Lui

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

摘要翻译： 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。

公开(公告)号：US08357973B2

公开(公告)日：2013-01-22

申请号：US13199382

申请日：2011-08-25

申请人： Sik K Lui ,  François Hébert ,  Anup Bhalla

发明人： Sik K Lui ,  François Hébert ,  Anup Bhalla

IPC分类号： H01L29/66

CPC分类号： H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉降通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

公开(公告)号：US08035159B2

公开(公告)日：2011-10-11

申请号：US11796985

申请日：2007-04-30

申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K Lui

发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K Lui

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

摘要翻译： 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。

公开(公告)号：US07436022B2

公开(公告)日：2008-10-14

申请号：US11413249

申请日：2006-04-29

申请人： Anup Bhalla ,  Daniel Ng ,  Sik K Lui

发明人： Anup Bhalla ,  Daniel Ng ,  Sik K Lui

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein the PN junction further includes a counter dopant region disposed in the epitaxial layer for reducing a sudden reversal of dopant profile near the PN junction for preventing an early breakdown in the PN junction.

摘要翻译： 本发明公开了一种半导体功率器件，其包括具有多个功率晶体管单元和接合势垒肖特基（JBS）区域的有源单元区域。 半导体功率器件包括JBS区域，其还包括多个肖特基二极管，每个肖特基二极管各自具有设置在半导体衬底的顶表面附近的外延层上的PN结，其中PN结还包括设置在外延层中的反掺杂剂区域 减少PN结附近的掺杂剂分布的突然反转，以防止PN结中的早期击穿。

公开(公告)号：US20080067584A1

公开(公告)日：2008-03-20

申请号：US11522669

申请日：2006-09-17

申请人： Sik K Lui ,  Francois Hebert ,  Anup Bhalla

发明人： Sik K Lui ,  Francois Hebert ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉陷通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。