公开(公告)号：US07476983B2

公开(公告)日：2009-01-13

申请号：US11358898

申请日：2006-02-21

申请人： Na-Rae Kim ,  Tae-Sik Son ,  Hee-Joong Oh ,  Byung-Heon Kwak ,  Jae-Hoon Joo ,  Hyung-Dong Kim ,  Young-Min Jang

发明人： Na-Rae Kim ,  Tae-Sik Son ,  Hee-Joong Oh ,  Byung-Heon Kwak ,  Jae-Hoon Joo ,  Hyung-Dong Kim ,  Young-Min Jang

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/40 ,  H01L23/58

CPC分类号： H01L24/03 ,  H01L22/32 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2224/48 ,  H01L2924/00

摘要： In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.

摘要翻译： 在衬垫的布局结构和用于半导体器件的测试或引线键合的衬垫的结构中，至少一个或多个非线接合焊盘的尺寸与至少一个或多个 用于半导体器件的引线接合的焊盘。 在焊盘结构中，焊盘包括导线接合区域，其具有用于在确定的焊盘尺寸内的顶部金属层的一部分的压花表面以改善接合过程，以及不具有压花表面的探针末端接触区域 在确定的焊盘尺寸内的顶部金属层的表面部分，以便在装置的测试期间减少探针尖端的磨损。 因此，可以在有限的区域内增加衬垫间距，并且可以在将在常规衬垫形成区域中占据的区域中进一步形成外围电路。 从而实现了半导体器件的更高集成度和探针尖端在探测中的磨损。

公开(公告)号：US5768174A

公开(公告)日：1998-06-16

申请号：US761300

申请日：1996-12-06

申请人： Dong-Il Seo ,  Hyung-Dong Kim

发明人： Dong-Il Seo ,  Hyung-Dong Kim

IPC分类号： G11C11/41 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  G11C5/06

CPC分类号： H01L27/105

摘要： Integrated circuit memory devices having metal straps include an array of memory devices arranged as a plurality of sub memory blocks (SMB) in a semiconductor substrate, and a plurality of sub word line drivers (SWD) disposed between adjacent sub memory blocks in the substrate. In particular, a plurality of first signal lines at a first metal level (M1) and extending in a first direction on the array are provided. The first signal lines are directly connected to a first sub word line driver at a face of the substrate. In addition, a plurality of second signal lines are provided at a first metal level (M1) and extend in a second direction, orthogonal to the first direction, from the first sub word line driver across at least one sub memory block SMB. At least one metal strap is also provided at a second metal level (M2), above the first metal level. The metal strap preferably crosses the plurality of first signal lines and extends from a first side of the first sub word line driver to a second opposing side of the first sub word line driver. Thus, it is unnecessary to provide the first signal lines at the second metal level or provide metal segments or islands to interconnect the first signal lines to metallization at the first metal level and to the first sub word line driver. Accordingly, the memory device of the present invention can be more highly integrated and less susceptible to defects caused by bridge "shorts".

摘要翻译： 具有金属带的集成电路存储器件包括布置在半导体衬底中的多个子存储器块（SMB）的存储器件阵列和设置在衬底中的相邻子存储块之间的多个子字线驱动器（SWD）。 特别地，提供了在第一金属级（M1）处并在阵列上沿第一方向延伸的多条第一信号线。 第一信号线在衬底的表面直接连接到第一子字线驱动器。 此外，多个第二信号线被设置在第一金属级（M1）处并且沿着与第一方向正交的第二方向从第一子字线驱动器跨越至少一个子存储器块SMB延伸。 在第一金属层上方的第二金属层（M2）上还设有至少一个金属带。 金属带优选地跨越多个第一信号线并且从第一子字线驱动器的第一侧延伸到第一副字线驱动器的第二相对侧。 因此，不需要在第二金属级提供第一信号线，或者提供金属段或岛以将第一信号线与第一金属级和第一子字线驱动器之间的金属化互连。 因此，本发明的存储器件可以更高度集成，并且不易受到桥“短路”引起的缺陷的影响。