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    Nonvolatile Memory Devices Including a Resistor Region
    21.
    发明申请
    Nonvolatile Memory Devices Including a Resistor Region 审中-公开
    包括电阻器区域的非易失性存储器件

    公开(公告)号：US20080246073A1

    公开(公告)日：2008-10-09

    申请号：US12138712

    申请日：2008-06-13

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L29/00

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES
    23.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES 有权
    非易失性半导体存储器件

    公开(公告)号：US20080135923A1

    公开(公告)日：2008-06-12

    申请号：US12031096

    申请日：2008-02-14

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    IPC分类号： H01L27/115 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

    摘要翻译： 非易失性存储器件包括在半导体衬底上的隧道绝缘层，电荷存储层，阻挡绝缘层和栅电极。 电荷存储层位于隧道绝缘层上，并且具有比隧道绝缘层更小的带隙，并且具有比半导体衬底更大的带隙。 阻挡绝缘层位于电荷存储层上，并且具有比电荷存储层更大的带隙，并且具有比隧道绝缘层更小的带隙。 栅电极位于阻挡绝缘层上。

    Non-volatile semiconductor memory devices
    25.
    发明申请
    Non-volatile semiconductor memory devices 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20080001212A1

    公开(公告)日：2008-01-03

    申请号：US11823397

    申请日：2007-06-27

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

    摘要翻译： 非易失性存储器件包括在半导体衬底上的隧道绝缘层，电荷存储层，阻挡绝缘层和栅电极。 电荷存储层位于隧道绝缘层上，并且具有比隧道绝缘层更小的带隙，并且具有比半导体衬底更大的带隙。 阻挡绝缘层位于电荷存储层上，并且具有比电荷存储层更大的带隙，并且具有比隧道绝缘层更小的带隙。 栅电极位于阻挡绝缘层上。

    METHOD OF FABRICATING TRAP NONVOLATILE MEMORY DEVICE
    26.
    发明申请
    METHOD OF FABRICATING TRAP NONVOLATILE MEMORY DEVICE 审中-公开
    TRAP非易失性存储器件的制造方法

    公开(公告)号：US20070059883A1

    公开(公告)日：2007-03-15

    申请号：US11459599

    申请日：2006-07-24

    申请人： Han-Mei CHOI ,  Chang-Hyun Lee ,  Seung-Hwan LEE ,  Young-Geun PARK ,  Sun-Jung KIM ,  Young-Sun KIM

    发明人： Han-Mei CHOI ,  Chang-Hyun Lee ,  Seung-Hwan LEE ,  Young-Geun PARK ,  Sun-Jung KIM ,  Young-Sun KIM

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L27/11568

    摘要： A method of fabricating a floating trap type nonvolatile memory device is provided. The method includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally annealing a resultant substrate including the cell gate insulating layer in a temperature range of 810-100° C.; and forming a gate electrode on the thermally annealed cell gate insulating layer.

    摘要翻译： 提供一种制造浮动阱型非易失性存储器件的方法。 该方法包括在半导体衬底上形成单元栅极绝缘层，该单元栅极绝缘层由下层绝缘层，电荷存储层和上部绝缘层构成; 在810-100℃的温度范围内热退火包含电池栅极绝缘层的所得衬底; 以及在所述热退火单元栅极绝缘层上形成栅电极。

    Finfets, nonvolatile memory devices including finfets, and methods of forming the same
    27.
    发明申请
    Finfets, nonvolatile memory devices including finfets, and methods of forming the same 有权
    Finfets，包括finfets的非易失性存储器件及其形成方法

    公开(公告)号：US20060292781A1

    公开(公告)日：2006-12-28

    申请号：US11473487

    申请日：2006-06-23

    申请人： Chang-Hyun Lee

    发明人： Chang-Hyun Lee

    IPC分类号： H01L21/8234 ,  H01L29/94

    CPC分类号： H01L29/7881 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

    摘要： A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device isolation layer and has a different thickness than the device isolation layer. A gate electrode crosses over the fin. A gate insulating layer is between the gate electrode and the fin. Source and drain regions are on the fins and on opposite sides of the gate electrode. Related nonvolatile memory devices that include FinFETs and methods of making FinFETs and nonvolatile memory devices are also disclosed.

    摘要翻译： FinFET包括在衬底上并且远离衬底延伸的翅片。 器件隔离层设置在鳍片两侧的衬底上。 绝缘层位于散热片和基板之间。 绝缘层直接连接到器件隔离层，并且具有与器件隔离层不同的厚度。 栅电极跨过鳍。 栅极绝缘层位于栅电极和鳍之间。 源极和漏极区域位于鳍状物和栅电极的相对侧上。 还公开了包括FinFET和制造FinFET和非易失性存储器件的方法的相关非易失性存储器件。

    Method of fabricating cell of nonvolatile memory device with floating gate
    28.
    发明授权
    Method of fabricating cell of nonvolatile memory device with floating gate 有权
    具有浮动栅极的非易失性存储器件单元制造方法

    公开(公告)号：US07122426B2

    公开(公告)日：2006-10-17

    申请号：US10788002

    申请日：2004-02-25

    申请人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

    发明人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

    摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

    摘要翻译： 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。