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110 条记录 (耗时 0.038 秒)

    INFORMATION RECORDING/REPRODUCING DEVICE
    24.
    发明申请
    INFORMATION RECORDING/REPRODUCING DEVICE 有权
    信息记录/再现设备

    公开(公告)号：US20110216576A1

    公开(公告)日：2011-09-08

    申请号：US13044384

    申请日：2011-03-09

    申请人： Shinya Aoki ,  Kohichi Kubo ,  Takayuki Tsukamoto ,  Takahiro Hirai ,  Chikayoshi Kamata ,  Tsukasa Nakai

    发明人： Shinya Aoki ,  Kohichi Kubo ,  Takayuki Tsukamoto ,  Takahiro Hirai ,  Chikayoshi Kamata ,  Tsukasa Nakai

    IPC分类号： G11C11/00 ,  H01L45/00

    CPC分类号： H01L45/1233 ,  G11B9/04 ,  G11C13/0011 ,  H01L27/101 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/146

    摘要： According to one embodiment, an information recording/reproducing device includes a recording layer and a driver section. The recording layer has a first layer including a first compound. The first compound includes a mixed crystal of a first oxide containing a first metallic element and a second oxide. The second oxide has a crystal structure being same as the first oxide and contains a second metallic element different from the first metallic element. The driver section is configured to produce state change in the recording layer to record information by at least one of application of voltage to the recording layer and passage of current to the recording layer. Composition ratio of an element having a smaller ionic radius of the first and second metallic elements is not less than percolation threshold of a lattice formed of ions of the first and second metallic elements based on the crystal structure.

    摘要翻译： 根据一个实施例，信息记录/再现装置包括记录层和驱动器部分。 记录层具有包含第一化合物的第一层。 第一化合物包括含有第一金属元素和第二氧化物的第一氧化物的混合晶体。 第二氧化物具有与第一氧化物相同的晶体结构，并且含有与第一金属元素不同的第二金属元素。 驱动器部分被配置为在记录层中产生状态变化，以通过施加电压至记录层和将电流流向记录层中的至少一个来记录信息。 基于晶体结构，第一和第二金属元素离子半径较小的元素的组成比不小于由第一和第二金属元素的离子形成的晶格的渗透阈值。

    Semiconductor device having first and second demodulation circuits for wireless communication
    27.
    发明授权
    Semiconductor device having first and second demodulation circuits for wireless communication 有权
    具有用于无线通信的第一和第二解调电路的半导体器件

    公开(公告)号：US08928400B2

    公开(公告)日：2015-01-06

    申请号：US13298897

    申请日：2011-11-17

    申请人： Takayuki Tsukamoto

    发明人： Takayuki Tsukamoto

    IPC分类号： H03D1/00 ,  H04L27/06 ,  H04B5/00

    CPC分类号： H04L27/06 ,  G06K7/0008 ,  H03D1/00 ,  H04B5/0031

    摘要： A device receives ASK signals by using an ASK signal receiving circuit that is different from an ASK signal receiving circuit for R/W mode, when an NFC-enabled semiconductor device operates in a mode other than the R/W mode. An ASK signal receiving circuit for 100% ASK is provided on the side of a pair of transmitting terminals. This arrangement eliminates the influence of an ESD provided within an ASK signal receiving circuit for 10% ASK coupled to a pair of receiving terminals. There is no need for management of threshold values that are different according to type of ASK and it is possible to support different modulation schemes by a smaller circuit configuration.

    摘要翻译： 当NFC功能半导体器件以除R / W模式之外的模式工作时，器件通过使用与用于R / W模式的ASK信号接收电路不同的ASK信号接收电路来接收ASK信号。 在一对发送端子的一侧设置有用于100％ASK的ASK信号接收电路。 这种布置消除了在与一对接收终端耦合的10％ASK的ASK信号接收电路内提供的ESD的影响。 不需要根据ASK的类型来管理不同的阈值，并且可以通过较小的电路配置来支持不同的调制方案。

    Nonvolatile semiconductor memory device
    28.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08675388B2

    公开(公告)日：2014-03-18

    申请号：US13233679

    申请日：2011-09-15

    申请人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

    发明人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2213/71

    摘要： A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

    摘要翻译： 非易失性半导体存储器件包括：包括多个第一线，多个第二线和多个存储单元的存储单元阵列，每个存储单元包括可变电阻元件; 第一解码器，连接到所述多条第一线的至少一端，并被配置为选择所述第一线中的至少一条线; 至少一对第二解码器，连接到所述多个第二线路的两端，并且被配置为使得所述一对第二解码器中的一个被选择用于根据所述第一线选择的所述第一线之间的距离来选择所述第二线 解码器和第二行的两端; 以及电压施加电路，被配置为在由第一解码器和第二解码器选择的第一线和第二线之间施加一定电压。

    Semiconductor integrated circuit and operating method thereof
    30.
    发明授权
    Semiconductor integrated circuit and operating method thereof 有权
    半导体集成电路及其操作方法

    公开(公告)号：US08374571B2

    公开(公告)日：2013-02-12

    申请号：US13279408

    申请日：2011-10-24

    申请人： Atsushi Motozawa ,  Takayuki Tsukamoto ,  Tatsuji Matsuura ,  Yuichi Okuda

    发明人： Atsushi Motozawa ,  Takayuki Tsukamoto ,  Tatsuji Matsuura ,  Yuichi Okuda

    IPC分类号： H04B1/28 ,  H04B1/06

    CPC分类号： H04B1/40 ,  H03H11/26 ,  H03K5/133

    摘要： An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.

    摘要翻译： 集成电路配备有接收混频器和信号发生器。 多级延迟电路响应于接收载波信号而产生多个时钟脉冲。 相位检测单元检测特定时钟脉冲的电压电平和在特定时钟脉冲之前产生的预定数量的时钟脉冲的电压电平之间的差异，从而检测特定时钟脉冲的预定相位。 时钟生成单元的选择器从时钟脉冲信号输出分别具有多个相位的多个选择时钟脉冲信号。 第一信号合成逻辑电路对选择时钟脉冲执行逻辑运算，从而产生提供给接收混频器的本地信号。