公开(公告)号：US08564045B2

公开(公告)日：2013-10-22

申请号：US13547399

申请日：2012-07-12

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L27/088 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.

摘要翻译： 公开了其阵列及其形成方法。 一个这样的存储器阵列具有与分离的基本上垂直的相邻半导体结构相邻的存储单元串，其中分离的半导体结构将各个串的存储单元串联耦合。 对于一些实施例，两个介电柱可以由在单个开口中形成的电介质形成，其中每个介电柱具有与其相邻的一对存储单元串，并且其中一个串中的至少一个存储单元位于 支柱和另一个支柱上的串中的一个的至少一个存储单元通常耦合到接入线。

公开(公告)号：US20130258779A1

公开(公告)日：2013-10-03

申请号：US13993312

申请日：2011-09-22

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： G11C16/02

CPC分类号： H01L27/11565 ,  G11C16/02 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mis-matched cell and bitline pitch. Other embodiments may be described and claimed.

摘要翻译： 本公开的实施例描述了具有错误匹配的单元和位线间距的NAND存储器阵列的方法，装置和系统配置。 可以描述和要求保护其他实施例。

公开(公告)号：US08289763B2

公开(公告)日：2012-10-16

申请号：US12795565

申请日：2010-06-07

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： G11C11/00

CPC分类号： G01R33/58 ,  G01R33/1284 ,  G01R33/24 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144

摘要： Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

摘要翻译： 一些实施例包括存储器阵列。 存储器阵列可以具有沿着第一水平方向延伸的全局位线，垂直于全局位线垂直延伸的垂直局部位线以及沿垂直于第一水平方向的第二水平方向延伸的字线。 全局位线可以在第一高度级细分为第一系列，而在第二高度级可以被分为与第一高度不同的第二系列。 第一个系列的全局位线可以与第二个系列的全局位线交替。 直接在字线和垂直的局部位线之间可以存储单元格材料。 存储单元材料可以形成由字线/全局位线组合唯一地寻址的多个存储单元。 一些实施例包括具有约2F2的面积的交叉点存储单元单元。

公开(公告)号：US20120181596A1

公开(公告)日：2012-07-19

申请号：US13206046

申请日：2011-08-09

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7926

摘要： Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

公开(公告)号：US07215577B2

公开(公告)日：2007-05-08

申请号：US11511763

申请日：2006-08-29

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/78

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

摘要翻译： 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

公开(公告)号：US06934190B1

公开(公告)日：2005-08-23

申请号：US10863933

申请日：2004-06-09

申请人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

发明人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths of individual dual bit memory cells within the memory device. To program a bit of a particular dual bit memory cell, a negative gate program voltage is applied to its gate, a positive drain voltage is applied to its acting drain, and its substrate is connected to ground. Additionally, a ramp source voltage of the range of ramp source program pulses is concurrently applied to an acting source of the dual bit memory cell. A verification operation is then performed and the programming is repeated with a decremented ramp source voltage on verification failure.

摘要翻译： 提供了包括具有一定范围值的编程的双位存储器件的操作方法。 本发明采用一系列斜坡源程序脉冲来迭代地执行采用热空穴注入的程序操作。 该范围与存储器件内的各个双位存储单元的通道长度有关。 为了编程一个特定的双位存储单元，负栅极编程电压被施加到其栅极，正的漏极电压被施加到其作用漏极，并且其衬底连接到地。 此外，斜坡源程序脉冲范围的斜坡源电压同时施加到双位存储单元的作用源。 然后执行验证操作，并且在验证失败时以递减的斜坡源电压重复编程。

公开(公告)号：US06834012B1

公开(公告)日：2004-12-21

申请号：US10863673

申请日：2004-06-08

申请人： Yi He ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Zengtao Liu ,  Mark William Randolph

发明人： Yi He ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Zengtao Liu ,  Mark William Randolph

IPC分类号： G11C1604

CPC分类号： G11C16/3404 ,  G11C16/0475

摘要： Methods of operating dual bit flash memory devices and correcting over-erased dual bit flash memory devices are provided. The present invention includes a corrective action that employs a negative gate to correct over-erased memory cells without substantially altering threshold voltage values or charge states for properly erased memory cells. The negative gate stress is performed as a block operation by applying a negative gate voltage to gates and connecting active regions and a substrate to ground.

摘要翻译： 提供了操作双位闪存器件和校正过擦除的双位闪存器件的方法。 本发明包括采用负栅极来校正过擦除的存储单元而没有基本上改变正确擦除的存储单元的阈值电压值或电荷状态的校正动作。 通过向栅极施加负栅极电压并将有源区域和衬底连接到地来执行负栅极应力作为块操作。