公开(公告)号：US06979608B2

公开(公告)日：2005-12-27

申请号：US10673874

申请日：2003-09-29

Applicant: Harry Contopanagos ,  Christos Komninakis ,  Sissy Kyriazidou

Inventor： Harry Contopanagos ,  Christos Komninakis ,  Sissy Kyriazidou

IPC: H04B1/40 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H04B1/406

Abstract: An on-chip inductor may be fabricated by creating at least one dielectric layer, creating at least one conductive winding on the at least one dielectric layer and creating: (1) a P-well layer having a major surface parallel to a major surface of the dielectric layer, (2) field oxide layer having a major surface parallel to a major surface of the dielectric layer, (3) P-well and field oxide layer, or (4) a poly-silicon layer having a major surface parallel to a major surface of the dielectric layer.

Abstract translation: 可以通过产生至少一个介电层来制造片上电感器，在至少一个电介质层上产生至少一个导电绕组，并产生：（1）P阱层，其主表面平行于 电介质层，（2）具有平行于电介质层的主表面的主表面的场氧化物层，（3）P阱和场氧化物层，或（4）主表面平行于 电介质层的主表面。

公开(公告)号：US06937128B2

公开(公告)日：2005-08-30

申请号：US10074158

申请日：2002-02-12

Applicant: Harry Contopanagos ,  Sissy Kyriazidou

Inventor： Harry Contopanagos ,  Sissy Kyriazidou

IPC: H01L27/08 ,  H01F5/00

CPC classification number: H01L27/08 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073

Abstract: An on-chip inductor and/or on-chip transformer includes at least one dielectric layer and at least one conductive winding on the at least one dielectric layer. The conductive winding has a substantially square geometry and has at least its exterior corners geometrically shaped to reduce impedance of the conductive winding at a particular operating frequency. Since the quality factor of an on-chip inductor is inversely proportional to the effective series impedance of an inductor at an operating frequency, by reducing the effective series impedance, the quality factor is increased.

Abstract translation: 片上电感器和/或片上变压器包括至少一个电介质层和至少一个电介质层上的至少一个导电绕组。 导电绕组具有基本上正方形的几何形状，并且至少具有几何形状的外部角，以减小导电绕组在特定工作频率下的阻抗。 由于片上电感的品质因数与工作频率下的电感器的有效串联阻抗成反比，通过降低有效串联阻抗，提高了品质因数。

公开(公告)号：US06907231B2

公开(公告)日：2005-06-14

申请号：US10122458

申请日：2002-04-15

Applicant: Iqbal S. Bhatti

Inventor： Iqbal S. Bhatti

IPC: H04B1/04 ,  H04Q11/12

CPC classification number: H04B1/0458

Abstract: An on-chip impedance matching includes a transistor, an inductor, and a capacitive divider. The gate of the transistor is operably coupled to receive input signals; the source of the transistor is coupled to a first DC voltage potential; and the drain of the transistor is operably coupled to the inductor. The other end of the inductor is operably coupled to a second DC voltage potential. The capacitive divider includes matched capacitors that, in combination with the inductor, provide for substantially lossless on-chip impedance matching, where a tap of the capacitive divider provides an output of the on-chip impedance matching power amplifier. In addition, the capacitance of the capacitive divider and the inductance of the inductor are tuned to provide a tank circuit for the on-chip impedance matching power amplifier.

Abstract translation: 片上阻抗匹配包括晶体管，电感和电容分压器。 晶体管的栅极可操作地耦合以接收输入信号; 晶体管的源极耦合到第一直流电压电位; 并且晶体管的漏极可操作地耦合到电感器。 电感器的另一端可操作地耦合到第二直流电压电位。 电容分压器包括匹配的电容器，其与电感器组合提供基本无损的片上阻抗匹配，其中电容分压器的抽头提供片上阻抗匹配功率放大器的输出。 此外，电容分压器的电容和电感的电感被调谐以提供用于片上阻抗匹配功率放大器的振荡电路。

公开(公告)号：US06882228B2

公开(公告)日：2005-04-19

申请号：US10657314

申请日：2003-09-08

Applicant: Ahmadreza (Reza) Rofougaran

Inventor： Ahmadreza (Reza) Rofougaran

IPC: H03F3/04 ,  H03F3/19 ,  H03F3/45 ,  H03F3/72

CPC classification number: H03F3/19 ,  H03F3/45071 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/372

Abstract: A radio frequency integrated circuit includes a power amplifier, a low noise amplifier, a first transformer balun, and a second transformer balun. The power amplifier includes a first power amplifier section and a second power amplifier section. When enabled, the first and second power amplifier sections amplify an outbound radio frequency (RF) signal to produce a first amplified outbound RF signal and a second amplified outbound RF signal, respectively. The power amplifier provides the first amplified outbound RF signal to the first transformer balun and the second outbound RF signal to the second transformer balun, where the first transformer balun is coupled to a first antenna and the second transformer balun is coupled to a second antenna. The low noise amplifier includes a first low noise amplifier section and a second low noise amplifier section. When enabled, the first low noise amplifier section amplifies a first inbound RF signal to produce a first amplified inbound RF signal, and, when enabled, the second low noise amplifier section amplifies a second inbound RF signal to produce a second amplified inbound RF signal. The low noise amplifier receives the first inbound RF signal from the first transformer balun and receives the second inbound RF signal from the second transformer balun.

Abstract translation: 射频集成电路包括功率放大器，低噪声放大器，第一变压器平衡 - 不平衡转换器和第二变压器平衡 - 不平衡变压器。 功率放大器包括第一功率放大器部分和第二功率放大器部分。 当使能时，第一和第二功率放大器部分放大出站射频（RF）信号以分别产生第一放大出站RF信号和第二放大出站RF信号。 功率放大器将第一变压器平衡 - 不平衡变换器的第一放大出站RF信号和第二变压器平衡 - 不平衡转换器的第二出站RF信号提供给第一变压器平衡 - 不平衡转换器，其中第一变压器平衡 - 不平衡变换器耦合到第一天线，并且第二变压器平衡 - 不平衡变换器耦合 低噪声放大器包括第一低噪声放大器部分和第二低噪声放大器部分。 当使能时，第一低噪声放大器部分放大第一入射RF信号以产生第一放大的入站RF信号，并且当使能时，第二低噪声放大器部分放大第二入射RF信号以产生第二放大入站RF信号。 低噪声放大器从第一变压器平衡 - 不平衡变换器接收第一入站RF信号，并从第二变压器平衡 - 不平衡转换器接收第二入站RF信号。

公开(公告)号：US20030210099A1

公开(公告)日：2003-11-13

申请号：US10404893

申请日：2003-04-01

Applicant: Broadcom Corp.

Inventor： Joseph M. Ingino JR.

IPC: H03B001/00

CPC classification number: H03L7/0995 ,  G05F3/262 ,  G05F3/30 ,  H03K3/0315 ,  H03K17/223 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/18

Abstract: A VCO for a PLL may include a ring oscillator having a power supply controlled in response to the VCO's control voltage input and an inverter having an input coupled to the ring oscillator's output and also supplied with a power supply controlled by the control voltage input. Together, the output of the ring oscillator and the output of the inverter may closely approximate a differential signal. The VCO may include an amplifier for amplifying a differential input to an output in the voltage domain of the system including the PLL. The output of the ring oscillator may be used as an input to the amplifier, and the output of the inverter may be used as the other input. The power supply terminals of the ring oscillator and the inverter may be coupled to outputs of a current mirror. In one implementation, the current mirror may not be cascoded.

公开(公告)号：US20030105828A1

公开(公告)日：2003-06-05

申请号：US10269922

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Barton J. Sano ,  Joseph B. Rowlands ,  Laurent R. Moll ,  Manu Gulati

IPC: G06F013/28 ,  G06F015/167

CPC classification number: G06F13/4022

Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Abstract translation: 装置可以包括第一系统和第二系统。 第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个被配置为耦合到单独的接口。 第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。 第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。 第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。

公开(公告)号：US20030097416A1

公开(公告)日：2003-05-22

申请号：US10270029

申请日：2002-10-11

Applicant: Broadcom Corp.

Inventor： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC: G06F015/167

CPC classification number: H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Abstract translation: 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些一致性命令来在互连上启动相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US1246748A

公开(公告)日：1917-11-13

申请号：US13080316

申请日：1916-11-11

Applicant: JOHNSON CARL

Inventor： JOHNSON CARL

CPC classification number: B65D49/00 ,  Y10T292/48

公开(公告)号：US07917114B2

公开(公告)日：2011-03-29

申请号：US11392868

申请日：2006-03-30

Applicant: Amit Bagchi ,  Rohit Gaikwad

Inventor： Amit Bagchi ,  Rohit Gaikwad

IPC: H04B1/06 ,  H04B7/00 ,  H04B1/28

CPC classification number: H03F1/26 ,  H03D3/008 ,  H03F1/34 ,  H03F3/24 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2200/294 ,  H03F2200/372 ,  H04B1/30

Abstract: The present invention relates to a DC offset canceling circuit. In one aspect of the invention, a DC offset canceling circuit with independently configurable gain and roll-off frequency is provided. In one embodiment of the present invention, the DC offset canceling circuit is used in the receive path of a down-conversion wireless receiver. In another aspect of the invention, a method for independently varying the gain and the roll-off frequency of the DC offset canceling circuit is provided. In one embodiment, the method is used to independently operate a gain control scheme and a DC offset cancellation strategy in a DC canceling circuit.

Abstract translation: 本发明涉及一种DC偏移抵消电路。 在本发明的一个方面，提供了具有独立可配置的增益和滚降频率的DC偏移消除电路。 在本发明的一个实施例中，DC偏移消除电路用于下变频无线接收机的接收路径。 在本发明的另一方面，提供一种用于独立地改变DC偏移消除电路的增益和滚降频率的方法。 在一个实施例中，该方法用于独立地操作DC消除电路中的增益控制方案和DC偏移消除策略。

公开(公告)号：US07895491B2

公开(公告)日：2011-02-22

申请号：US11418588

申请日：2006-05-04

Applicant: Yuqian C. Wong

Inventor： Yuqian C. Wong

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318575

Abstract: An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern of data into the loading circuit without powering the combinational logic of the IC-LPBIST, wherein the shift test pattern of data is configured to test the combinational logic for logical faults.

Abstract translation: 公开了具有低功率内置自检逻辑（“IC-LPBIST”）的集成电路。 IC-LPBIST可以包括组合逻辑和加载电路，其能够将数据的移位测试模式加载到加载电路中，而不对IC-LPBIST的组合逻辑进行供电，其中数据的移位测试模式被配置为测试组合逻辑 用于逻辑故障。