公开(公告)号：US20090108955A1

公开(公告)日：2009-04-30

申请号：US12083573

申请日：2006-10-10

Applicant: Kanji Otsuka ,  Munekazu Takano ,  Fumio Mizuno ,  Saburo Yokokura ,  Tsuneo Ito ,  Yuko Tanba ,  Yutaka Akiyama

Inventor： Kanji Otsuka ,  Munekazu Takano ,  Fumio Mizuno ,  Saburo Yokokura ,  Tsuneo Ito ,  Yuko Tanba ,  Yutaka Akiyama

IPC: H03K5/1252 ,  H01L29/94

CPC classification number: H03K5/156 ,  H01L23/642 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/19041 ,  H01L2924/19051 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03K2005/00026 ,  H03K2217/0018 ,  H04L25/085 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection 20 for transmission of signals, a MOS capacitance element 10 having a gate electrode connected to the signal-transmission interconnection 20, a first voltage-applying interconnection 30 connected to a source and a drain of the MOS capacitance element 10 and applying a voltage to the source and the drain of the MOS capacitance element 10, a second voltage-applying interconnection 40 connected to a well of the MOS capacitance element 10, and applying a voltage to the well of said first MOS capacitance element 10. Jitters occurring in the signal-transmission interconnection 20 can be adjusted by adjusting each of voltages of the first voltage-applying interconnection 30 and the second voltage-applying interconnection 40.

Abstract translation: 本发明的目的是提供一种半导体器件，其包括优选用于传输高频信号的信号传输互连和调整上述信号传输互连特性的能力。 根据本发明的半导体器件包括用于传输信号的信号传输互连20，具有连接到信号传输互连20的栅电极的MOS电容元件10，连接到源的第一施加电压互连30 和MOS电容元件10的漏极，并向MOS电容元件10的源极和漏极施加电压，连接到MOS电容元件10的阱的第二施加电压互连40，并向 可以通过调节第一施加电压互连30和第二施加电压互连40的每个电压来调节发生在信号传输互连20中的抖动。

公开(公告)号：US20080231331A1

公开(公告)日：2008-09-25

申请号：US11726911

申请日：2007-03-22

Applicant: Vishnu Balraj ,  Terry Baucom ,  Amir Bashir ,  Huimin Chen ,  Ken Drottar ,  Naveed Khan ,  Duane Quiet ,  Andrew M. Volk

Inventor： Vishnu Balraj ,  Terry Baucom ,  Amir Bashir ,  Huimin Chen ,  Ken Drottar ,  Naveed Khan ,  Duane Quiet ,  Andrew M. Volk

IPC: H03L7/00

CPC classification number: H03L7/08 ,  G06F1/04 ,  H03K5/156 ,  H03K7/06

Abstract: Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Abstract translation: 公开了用于产生扩频时钟的方法和电路的实施例。

公开(公告)号：US20080136470A1

公开(公告)日：2008-06-12

申请号：US11985340

申请日：2007-11-13

Applicant: Nathan Moyal ,  Jonathon Stiff

Inventor： Nathan Moyal ,  Jonathon Stiff

IPC: H03L7/00

CPC classification number: H03K5/135 ,  H03K5/156

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract translation: 用于对准包括第一和第二信号的两个或多个信号的电路和方法。 在一个实施例中，移位寄存器产生第二信号的两个或更多个偏移副本，并且多个相位检测器中的每一个接收第一信号和第二信号的移位副本之一，每个相位检测器提供一个输出， 第一信号基本上与第二信号的偏移副本对准。 还可以提供多路复用器用于接收第二信号的每个移位副本，多路复用器具有与相位检测器的输出信号耦合的多条选择线。 一些实施例可以包括省电模式。

公开(公告)号：US07352204B2

公开(公告)日：2008-04-01

申请号：US11413717

申请日：2006-04-28

Applicant: Arnold M. Frisch

Inventor： Arnold M. Frisch

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K5/156 ,  G01R31/31706 ,  G01R31/31725 ,  H03K5/151 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/085

Abstract: A skew correction system incorporated into a transmitter forwarding a differential signal on a differential lane monitors returning signal reflections when the receiving end of the differential lane is appropriately terminated. Based on an analysis of the reflections, the skew correction system adjusts the relative timing of complementary edges of the differential signal departing the transmitter so as to substantially eliminate skew at the receiving end of the differential lane.

Abstract translation: 在差分通道上转发差分信号的发送器中的偏斜校正系统监视差分通道的接收端适当地终止时的返回信号反射。 基于对反射的分析，偏斜校正系统调整离开发射机的差分信号的互补边缘的相对定时，以便基本上消除差分通道接收端的偏移。

公开(公告)号：US07348863B2

公开(公告)日：2008-03-25

申请号：US11176029

申请日：2005-07-06

Applicant: Mark Kintis ,  Flavia S. Fong

Inventor： Mark Kintis ,  Flavia S. Fong

IPC: H03K3/017 ,  H03K3/02 ,  H03K12/00 ,  H04B3/02

CPC classification number: H03K5/12 ,  H03K5/06 ,  H03K5/156

Abstract: A pulse generating circuit and related method, for producing extremely narrow pulses for use in monolithic microwave integrated circuits (MMICs) for radar, high-speed sampling, pulse radio and other applications. A sinusoidal input signal is supplied to two nonlinear shock wave generators, which are oppositely biased to produce periodic outputs that are mirror images of each other, one with a very steep rising edge and one with a very steep falling edge. The combined outputs would cancel each other completely but for the introduction of a slight time delay in one of them, which results in a narrow peak in the combined signals.

Abstract translation: 脉冲发生电路和相关方法，用于产生用于雷达，高速采样，脉冲无线电和其他应用的单片微波集成电路（MMIC）中的极窄脉冲。 正弦输入信号被提供给两个非线性冲击波发生器，它们被相反地偏置以产生彼此是镜像的周期性输出，一个具有非常陡峭的上升沿，一个具有非常陡峭的下降沿。 组合的输出将完全相互抵消，但是在其中一个中引入轻微的时间延迟，这导致组合信号中的峰值较小。

公开(公告)号：US20070252628A1

公开(公告)日：2007-11-01

申请号：US11790601

申请日：2007-04-26

Applicant: Ichiro Abe

Inventor： Ichiro Abe

IPC: H03K3/017

CPC classification number: H03K5/156 ,  H03K5/01

Abstract: Disclosed is waveform width adjusting circuit that comprises: a delay circuit having a prescribed delay time is provided in a signal propagation path and a delay adjusting circuit which applies an adjustment in such a manner that when a waveform width extending from either a positive-going transition or a negative-going transition of the signal waveform at an input terminal to the next negative-going transition or positive-going transition is greater than the delay time of the delay circuit, a signal having a reduced waveform width is output, and such that when the waveform width of the signal at the input terminal is less than or equal to the delay time, the waveform width is not reduced and the signal that is output has the waveform width of the original signal. Thus, the waveform width of a signal for which the waveform width is less than a limit is not reduced.

Abstract translation: 公开了一种波形宽度调整电路，包括：在信号传播路径中设置具有规定延迟时间的延迟电路，延迟调整电路以这样的方式进行调整：当从正向转变 或者在输入端子处的信号波形向下一个负向转换或正向转变的负向转变大于延迟电路的延迟时间，则输出具有减小的波形宽度的信号，并且使得 当输入端子的信号的波形宽度小于或等于延迟时间时，波形宽度不减小，输出的信号具有原始信号的波形宽度。 因此，波形宽度小于极限的信号的波形宽度不降低。

公开(公告)号：US20070013422A1

公开(公告)日：2007-01-18

申请号：US11179400

申请日：2005-07-12

Applicant: Quanhong Zhu ,  Don D. Josephson

Inventor： Quanhong Zhu ,  Don D. Josephson

IPC: H03K3/017

CPC classification number: H03K5/156 ,  H03K5/05 ,  H03K2005/00156

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract translation: 在一个实施例中，时钟脉冲宽度控制电路包括多个定时器电路，以从输入时钟信号，对应的多个与门产生相应的多个延迟脉冲信号，每个与门从延迟脉冲产生输出信号 信号和输入时钟信号，以及选择电路以选择输出信号之一。

公开(公告)号：US20060267650A1

公开(公告)日：2006-11-30

申请号：US11439405

申请日：2006-05-22

Applicant: Hisao Takahashi

Inventor： Hisao Takahashi

IPC: H03K5/12

CPC classification number: H03K5/135 ,  G01R31/31709 ,  H03K5/156

Abstract: Fast data patterns with desired edge positions are provided. A pattern generator (PG) circuit 10 stores and provides data patterns and respective position control data. A delay circuit 16 delays a clock CLK to produce a position control clock according to the position control data. An output flip flop 18 provides the data patterns following to the position control clock. The position of the clock is controlled as an operation reference of the data pattern and, as a result, controls the edge positions of the output data pattern.

公开(公告)号：US20060202731A1

公开(公告)日：2006-09-14

申请号：US11371043

申请日：2006-03-09

Applicant: Akira Takahashi ,  Jiro Miyake ,  Toru Morikawa

Inventor： Akira Takahashi ,  Jiro Miyake ,  Toru Morikawa

IPC: G06F1/04

CPC classification number: H03K5/156 ,  G06F1/04 ,  H03K5/15013

Abstract: A clock signal is provided with amplitudes of a plurality of levels and flip-flop circuits having different threshold values are used so that at least two different frequencies can be simultaneously supplied through one clock signal line.

Abstract translation: 时钟信号被提供有多个电平的幅度，并且使用具有不同阈值的触发器电路，使得可以通过一个时钟信号线同时提供至少两个不同的频率。

公开(公告)号：US20060139082A1

公开(公告)日：2006-06-29

申请号：US11315236

申请日：2005-12-23

Applicant: Stefan Schabel

Inventor： Stefan Schabel

IPC: G06F1/04

CPC classification number: H03K5/135 ,  H03K5/04 ,  H03K5/133 ,  H03K5/156 ,  H03L7/0995

Abstract: A method for generating a pulse train is provided with adjustable start and end times of individual pulses, in which additional clock signals are generated from a 0th clock signal, the signals which in each case have a frequency of the 0th clock signal and whose phase is shifted in each case relative to a phase of the 0th clock signal. Pairs of one first clock signal and one second clock signal are provided, partial pulses are generated from the properties of the first and second clock signal of a pair in accordance with a timing vector, and the pulse train is generated by superimposition of partial pulses.

Abstract translation: 提供了一种用于产生脉冲串的方法，其具有可调节的各个脉冲的开始和结束时间，其中从第0时钟信号产生附加的时钟信号，每个时钟信号在每种情况下具有第0个时钟信号的频率， 在每种情况下相对于第0个时钟信号的相位移位。 提供一对第一时钟信号和一个第二时钟信号，根据定时向量从一对的第一和第二时钟信号的属性产生部分脉冲，并且通过部分脉冲的叠加产生脉冲串。