公开(公告)号：US06920182B2

公开(公告)日：2005-07-19

申请号：US09757798

申请日：2001-01-09

申请人： Jerry Thomas Bolton, Jr.

发明人： Jerry Thomas Bolton, Jr.

IPC分类号： H03L7/197 ,  H03M3/02

CPC分类号： H03L7/1976 ,  H03M3/50 ,  H03M7/3008 ,  H03M7/3022

摘要： The invention discloses a system and method for improving the out-of-band noise response of a multi-order delta-sigma modulator. The system and method includes programmable delta-sigma modulators which may be programmed to vary the reference signals at each modulator stage subsequent to the first stage relative to the reference signal of the first modulator stage. The resulting signal output will then typically exhibit the enhanced noise suppression characteristics of a dithered signal without the added circuitry and power required of a dithering apparatus.

摘要翻译： 本发明公开了一种用于改进多阶Δ-Σ调制器的带外噪声响应的系统和方法。 该系统和方法包括可编程Δ-Σ调制器，其可编程为相对于第一调制器级的参考信号在第一级之后的每个调制器级改变参考信号。 然后，所得到的信号输出通常将呈现抖动信号的增强的噪声抑制特性，而不需要增加的电路和抖动装置所需的功率。

公开(公告)号：US20050017887A1

公开(公告)日：2005-01-27

申请号：US10495863

申请日：2003-08-27

申请人： Yoichi Nagaso ,  Takaharu Saeki

发明人： Yoichi Nagaso ,  Takaharu Saeki

IPC分类号： H03M1/20 ,  H03L7/183 ,  H03L7/197 ,  H03M1/08 ,  H03M3/00 ,  H03M3/02 ,  H03M7/00 ,  H03M7/36 ,  H04B14/06

CPC分类号： H03M7/3008 ,  H03L7/1978 ,  H03M7/3042

摘要： A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ΔΣ modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator (33) receives a particular F value (e.g., F=2n−1).

摘要翻译： 分数分频器（28）包括用于保持分频数据的锁存器（31），DeltaSigma调制器（33），数字抖动电路（32），用于从锁存器接收代表分频数据的分数部分的数字输入F （31），并且向Delta-Σ调制器（33）提供在F + k和Fk（其中k是整数）或F值本身之间交替变化的数字输出，以及用于执行基于分数分频的电路装置（34至38） 分频数据的整数部分（M值）和Delta-Σ调制器（33）的输出。 数字抖动电路（32）可用于抑制当DeltaSigma调制器（33）接收到特定的F值（例如，F = 2 ）时由于特定频率处的量化噪声的集中而产生的寄生信号 ）。

公开(公告)号：US5986512A

公开(公告)日：1999-11-16

申请号：US989864

申请日：1997-12-12

申请人： H.ang.kan Bengt Eriksson

发明人： H.ang.kan Bengt Eriksson

IPC分类号： H03C3/00 ,  H03C3/09 ,  H03L7/183 ,  H03L7/197 ,  H03M7/00 ,  H04B14/06 ,  H04L27/12 ,  H04L27/20 ,  H03K23/68

CPC分类号： H03M7/3008 ,  H03L7/1976 ,  H04L27/2017 ,  H03C3/0908 ,  H03M7/3022 ,  H03M7/304

摘要： A .SIGMA..DELTA. modulator-controlled, phase-locked-loop circuit, and an associated method, generates a frequency-regulated signal which does not exhibit undesired tones. Dithering signals are generated and are provided to a .SIGMA..DELTA. modulator. The .SIGMA..DELTA. modulator forms a division-factor control signal used to control the division factor of a frequency divider forming a portion of the PLL circuit. The dithering signals applied to the .SIGMA..DELTA. modulator reduce the likelihood that the .SIGMA..DELTA. modulator shall enter a limit cycle and generate repetitive output signals.

摘要翻译： SIGMA DELTA调制器控制的锁相环电路和相关联的方法产生不显示不需要的音调的频率调节信号。 产生抖动信号并提供给SIGMA DELTA调制器。 SIGMA DELTA调制器形成分频因子控制信号，用于控制形成PLL电路的一部分的分频器的分频系数。 施加到SIGMA DELTA调制器的抖动信号降低了SIGMA DELTA调制器进入极限周期并产生重复输出信号的可能性。

公开(公告)号：US5191331A

公开(公告)日：1993-03-02

申请号：US818522

申请日：1992-01-09

申请人： Teppo Karema ,  Hannu Tenhunen ,  Tapani Ritoniemi

发明人： Teppo Karema ,  Hannu Tenhunen ,  Tapani Ritoniemi

IPC分类号： H03M3/02 ,  H03M7/00

CPC分类号： H03M7/3008 ,  H03M7/304

摘要： The invention relates to a digital sigma-delta modulator for a D/A converter, comprising an integration stage or several cascaded integration stages and a feedback circuit for feedbacking the sign of the output signal of the last integration stage, delayed by one clock cycle and multiplied by a predetermined scaling coefficient, to each integration stage. To avoid limit cycle oscillation, the state of at least the least significant free bit in at least one integration stage is variable at random.

摘要翻译： 本发明涉及用于D / A转换器的数字Σ-Δ调制器，其包括积分级或多级联积分级和反馈电路，用于反馈最后一个积分级的输出信号的符号，延迟一个时钟周期， 乘以预定的缩放系数到每个积分级。 为了避免极限循环振荡，至少一个积分级中至少最低有效空闲位的状态是随机变化的。

公开(公告)号：US20230412191A1

公开(公告)日：2023-12-21

申请号：US18246446

申请日：2020-09-28

申请人： EATON INTELLIGENT POWER LIMITED

发明人： Daniel ZUCCHETTO ,  Niall CAHILL ,  Keith NOLAN

IPC分类号： H03M7/30 ,  H03M7/32

CPC分类号： H03M7/3059 ,  H03M7/3008

摘要： A method for compressing a signal, the method comprising: acquiring, via a signal recording module, a primary signal; modelling, via a processor, a model signal of the primary signal by: acquiring, via the processor, a sampled signal; acquiring, via the processor, a windowed signal; and extracting, via the processor: a fundamental frequency waveform having a fundamental magnitude and a fundamental phase; and at least one harmonic frequency waveform having a harmonic magnitude and a harmonic phase; wherein the model signal comprises the fundamental frequency waveform and the at least one harmonic frequency waveform; calculating, via the processor, an error signal between a reconstructed signal and the primary signal; determining, via the processor, an optimal gain from at least; an averaging step providing an average value, a predefined threshold, and a scaled signal.

公开(公告)号：US20190149165A1

公开(公告)日：2019-05-16

申请号：US16098652

申请日：2017-04-25

申请人： D&M Holdings, Inc.

发明人： Rainer Finck ,  Shozo Kawahara

IPC分类号： H03M3/00 ,  H03M1/08 ,  H03M7/32

CPC分类号： H03M3/504 ,  H03M1/0863 ,  H03M7/3008

摘要： A bitstream converter for converting a 1-bit pulse density modulated (PDM) bitstream signal into an analog audio signal, the bitstream converter comprising: a processor configured to process the 1-bit PDM bitstream signal using a return to zero clock having a frequency higher than a sampling frequency of the 1-bit PDM bitstream signal to output a corresponding 1-bit return to zero signal, wherein the processor is configured to process the 1-bit PDM signal to ensure a portion of each bit of the 1-bit PDM bitstream signal is zero for a duration which is based on the frequency of the return to zero clock; and signal processing means configured to extract the analog audio signal from the 1-bit return to zero signal by filtering the 1-bit return to zero signal.

公开(公告)号：US08730076B2

公开(公告)日：2014-05-20

申请号：US13561507

申请日：2012-07-30

申请人： Hashem Zare-Hoseini ,  Shuja Hussain Andrabi

发明人： Hashem Zare-Hoseini ,  Shuja Hussain Andrabi

IPC分类号： H03M1/20

CPC分类号： H03M7/3008

摘要： A circuit for modulating an input signal including a dither signal generator configured to generate a first dither signal having a maximum amplitude, a deamplifier configured to reduce the amplitude of said input signal so as to generate a deamplified input signal having a maximum amplitude that is comparable to the maximum amplitude of the dither signal, and a summer configured to sum the dither signal with the deamplified input signal.

摘要翻译： 一种用于调制包括被配置为产生具有最大幅度的第一抖动信号的抖动信号发生器的输入信号的电路，被配置为减小所述输入信号的幅度以便产生具有可比较的最大振幅的去放大输入信号的去放大器 到抖动信号的最大幅度，以及加法器，用于将抖动信号与去放大的输入信号相加。

公开(公告)号：US20070252737A1

公开(公告)日：2007-11-01

申请号：US11570580

申请日：2005-06-23

申请人： Johannes Eikenbroek

发明人： Johannes Eikenbroek

IPC分类号： H03M3/02

CPC分类号： H03L7/1976 ,  H03M3/328 ,  H03M3/424 ,  H03M3/438 ,  H03M7/3008 ,  H03M7/3026 ,  H03M7/3033

摘要： A method of generating a quantized signal in a Sigma-Delta modulator (25) comprises the steps of feeding a modulator input signal to a quantizer (15) via at least one integrator (12, 13); generating in the quantizer (15) a quantized signal; feeding back the quantized signal to be subtracted from the modulator input signal; and generating a dither signal to be applied to a point in the Sigma-Delta modulator. The dither signal is applied to a selected one of a number of different points (11, 14) in the Sigma-Delta modulator (25) in dependence of a control signal. In this way a method of generating a quantized signal in a Sigma-Delta modulator is provided which provides optimal results for different modes of the application, such as phase modulation mode and frequency modulation mode in a Bluetooth receiver.

摘要翻译： 在Σ-Δ调制器（25）中产生量化信号的方法包括以下步骤：通过至少一个积分器（12,13）将调制器输入信号馈送到量化器（15）; 在量化器（15）中生成量化信号; 反馈要从调制器输入信号中减去的量化信号; 并产生要施加到Σ-Δ调制器中的点的抖动信号。 根据控制信号，抖动信号被施加到Σ-Δ调制器（25）中的多个不同点（11,14）中的一个选择的一个。 以这种方式，提供了在Σ-Δ调制器中产生量化信号的方法，其为不同的应用模式提供了最佳结果，例如蓝牙接收机中的相位调制模式和调频模式。

公开(公告)号：US20070122048A1

公开(公告)日：2007-05-31

申请号：US11339123

申请日：2006-01-25

申请人： Sebastien Fievet

发明人： Sebastien Fievet

IPC分类号： G06K9/00 ,  H03M7/00

CPC分类号： H03M1/066 ,  G06K9/6282 ,  H03M1/0668 ,  H03M3/464 ,  H03M3/502 ,  H03M7/3008

摘要： A method and system for quantizing a vector corresponding to an input signal is described. The vector has a plurality of components corresponding to an N-dimensional space. In one aspect, the method and system include recursively dividing the space into equal spaces having one dimension less than a previous recursion until end spaces are formed. Each end space is two-dimensional. The method and system also include asynchronously comparing the components in each end space to determine a sub-space of a particular end space having a closest match to the vector. In another aspect, the method and system include providing tree(s) including a plurality of nodes and asynchronously traversing the tree(s) to determine a closest match to the vector. The nodes correspond to ANDs of comparisons between the components. Each comparison determines whether a first component is greater than a second component.

摘要翻译： 描述用于量化对应于输入信号的向量的方法和系统。 矢量具有对应于N维空间的多个分量。 在一个方面，方法和系统包括将空间递归地分成等于具有小于先前递归的维度的空间，直到形成最终空格。 每个结束空间都是二维的。 该方法和系统还包括异步地比较每个结束空间中的组件，以确定具有与向量最接近的匹配的特定终端空间的子空间。 在另一方面，所述方法和系统包括提供包括多个节点的树，并且异步地遍历所述树以确定与所述向量最接近的匹配。 节点对应于组件之间的比较的AND。 每个比较确定第一分量是否大于第二分量。

公开(公告)号：US06941333B2

公开(公告)日：2005-09-06

申请号：US10079800

申请日：2002-02-20

申请人： Makoto Akune ,  Yasuhiro Ogura

发明人： Makoto Akune ,  Yasuhiro Ogura

IPC分类号： G10L11/00 ,  G10L21/02 ,  H03M7/32 ,  G06F17/17 ,  G06F17/10

CPC分类号： H03M7/3008 ,  H03M7/3028 ,  H03M7/304

摘要： A normalizer normalizes the power of a dither signal calculated by a power calculator based on the average power of a PCM signal in the range of 18 kHz to 20 kHz, wherein the average power is calculated by the power calculator. An oversampling processor oversamples the PCM signal with a quantization frequency of 44.1 kHz and a quantization word length of 16 bits, wherein the PCM signal is inputted from an input terminal at a sampling frequency of 2×44.1 kHz, and then supplies an output of the oversampling process to an adder. The adder adds the normalized output from the normalizer to the oversampling output from the oversampling processor, and then supplies the addition output to an oversampling processor.

摘要翻译： 归一化器根据功率计算器根据PCM信号在18kHz至20kHz范围内的平均功率计算出的抖动信号的功率进行归一化，其中平均功率由功率计算器计算。 过采样处理器以44.1kHz的量化频率和16位的量化字长度对PCM信号进行过采样，其中PCM信号以2x44.1kHz的采样频率从输入端输入，然后提供 过采样处理到加法器。 加法器将归一化器的归一化输出与过采样处理器的过采样输出相加，然后将加法输出提供给过采样处理器。