公开(公告)号：US09304568B2

公开(公告)日：2016-04-05

申请号：US14351456

申请日：2012-10-11

申请人： Rambus Inc.

发明人： Yu Chang ,  Lei Luo ,  Kyung Suk Oh

IPC分类号： H04B1/04 ,  G06F1/32 ,  G06F1/30

CPC分类号： G06F1/32 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

摘要： Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

摘要翻译： 公开的实施例涉及改变发射机和/或接收机设置以处理由诸如功率状态或时钟启动事件的改变等预定事件引起的可靠性问题的系统。 一个实施例在正常操作模式期间操作发射机时使用第一设置，以及在预定事件之后的过渡期间操作发射机时的第二设置。 第二实施例在接收机中使用类似的第一和第二设置，或在双向链路的一侧采用的发射机和接收机两者中。第一和第二设置可以与不同的摆动电压，边缘速率，均衡和/或阻抗相关联 。

公开(公告)号：US20160091918A1

公开(公告)日：2016-03-31

申请号：US14499152

申请日：2014-09-27

申请人： QUALCOMM Incorporated

发明人： Francois Ibrahim ATALLAH ,  David Joseph Winston HANSQUINE ,  Richard Duane TAX ,  Robert Simpson TAYLOR

IPC分类号： G06F1/10 ,  H03K3/012

CPC分类号： G06F1/10 ,  G06F1/32 ,  G06F1/3237 ,  H03K3/012 ,  H03K19/0008 ,  H03K19/0019 ,  Y02D10/128

摘要： Systems and methods are directed to a configurable last level driver coupled to a inductor-capacitor (LC) tank or resonant clock, for improving energy efficiency of the resonant clock. In a warm up stage, the last level clock driver can be enabled to store energy in the LC tank, and in a gating stage, the last level clock driver can be fully or partially disabled such that energy stored in the LC tank can be recirculated into a clock distribution network. In a refreshing stage, the last level clock driver can be enabled to replenish the energy lost by the LC tank in the recirculation of energy into the clock distribution network during the gating stage. Programmable counters can be used to control durations of the warm up, gating, and refreshing stages.

摘要翻译： 系统和方法涉及耦合到电感器 - 电容器（LC）箱或谐振时钟的可配置的最后级别驱动器，用于提高谐振时钟的能量效率。 在预热阶段，最后一级时钟驱动器可以使能在LC箱中存储能量，并且在选通阶段，最后一级时钟驱动器可以被完全或部分禁用，使得储存在LC箱中的能量可以再循环 进入时钟分配网络。 在更新阶段，可以启用最后一级时钟驱动器，以便在门控阶段期间将能量损失的能量补充到能量进入时钟分配网络中。 可编程计数器可用于控制预热，门控和刷新阶段的持续时间。

公开(公告)号：US20160048191A1

公开(公告)日：2016-02-18

申请号：US14459482

申请日：2014-08-14

申请人： Apple Inc.

发明人： Erik P. Machnicki ,  Gilbert H. Herbeck ,  Shu-Yi Yu ,  Sebastian Skalberg

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： A system and method for managing idleness of functional units in an IC is disclosed. An IC includes a subsystem having a number of functional units and an idle aggregation unit. When a particular functional unit determines that it is idle, it may assert an idle indication to the idle aggregation unit. When the respective idle indications are concurrently asserted for all of the functional units, the idle aggregation unit may assert and provide respective idle request signals to each of the functional units. Responsive to receiving an idle request unit, a given functional unit may provide an acknowledgement signal to the idle aggregation unit if no transactions are incoming. If all functional units have concurrently asserted their respective acknowledgement signals, the idle aggregation unit may provide an indication of the same to a clock gating unit, which may then gate the clock signal(s) received by the functional units.

摘要翻译： 公开了一种用于管理IC中的功能单元的空闲的系统和方法。 IC包括具有多个功能单元和空闲聚合单元的子系统。 当特定功能单元确定它是空闲时，它可以向空闲聚合单元断言空闲指示。 当对于所有功能单元同时断言相应的空闲指示时，空闲汇聚单元可以向每个功能单元断言并提供相应的空闲请求信号。 响应于接收空闲请求单元，如果没有事务进入，则给定功能单元可以向空闲聚合单元提供确认信号。 如果所有功能单元已经同时确定其各自的确认信号，则空闲聚合单元可以向时钟选通单元提供相同的指示，时钟门控单元然后可以对由功能单元接收的时钟信号进行门控。

公开(公告)号：US20160011645A1

公开(公告)日：2016-01-14

申请号：US14679828

申请日：2015-04-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JUNGHI MIN

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172

摘要： Provided is a control method of a system-on-chip including a multi-core processor. The control method includes detecting a rate of runnable tasks to be performed in the multi-core processor and a driving voltage or a driving clock of the multi-core processor, determining whether variation of the rate of the runnable tasks sampled from a first time point to a current time and variation of the driving voltage or the driving clock sampled from a second time point to the current time satisfy a hotplug condition, and hotplugging in or out at least one core included in the multi-core processor when the rate of the runnable tasks and the driving voltage or the driving clock each satisfy the hotplug condition.

摘要翻译： 提供了包括多核处理器的片上系统的控制方法。 控制方法包括：检测要在多核处理器中执行的可运行任务的速率和多核处理器的驱动电压或驱动时钟，确定从第一时间点采样的可运行任务的速率是否变化 当前时间和从第二时间点到当前时间采样的驱动电压或驱动时钟的变化满足热插拔条件，并且当包含在多核处理器中的速率时热插拔输入或输出包含在多核处理器中的至少一个核心 运行任务和驱动电压或驱动时钟均满足热插拔条件。

公开(公告)号：US20150379673A1

公开(公告)日：2015-12-31

申请号：US14712675

申请日：2015-05-14

申请人： Samsung Electronics Co., Ltd.

发明人： Karthik Ramani ,  Kwontaek Kwon ,  John W. Brothers

IPC分类号： G06T1/20 ,  G06F1/32

CPC分类号： G06F1/3293 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F17/17 ,  G06T1/20 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171

摘要： Signal processing may include determining a first component common to a first input signal and a second input signal and extracting the first component from at least one of the first input signal or the second input signal, a second component from the first input signal, and a second component from the second input signal. The second component of the first input signal may be different from the second component of the second input signal. An operation may be performed using the extracted, second components. The first component may be combined with a result of the operation.

摘要翻译： 信号处理可以包括确定第一输入信号和第二输入信号共同的第一分量，并从第一输入信号或第二输入信号中的至少一个提取第一分量，从第一输入信号中提取第二分量，以及 第二分量来自第二输入信号。 第一输入信号的第二分量可以不同于第二输入信号的第二分量。 可以使用提取的第二组件来执行操作。 第一个组件可以与操作的结果相结合。

公开(公告)号：US09218046B2

公开(公告)日：2015-12-22

申请号：US14564436

申请日：2014-12-09

申请人： INTEL CORPORATION

发明人： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F9/50 ,  G06F12/08

CPC分类号： G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

摘要： An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

摘要翻译： 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。

公开(公告)号：US09134787B2

公开(公告)日：2015-09-15

申请号：US13360559

申请日：2012-01-27

申请人： Matthew Raymond Longnecker ,  Scott Alan Williams ,  Sagheer Ahmad ,  Robert Alan Bignell ,  Venkata Krishna Reddy Dumpa

发明人： Matthew Raymond Longnecker ,  Scott Alan Williams ,  Sagheer Ahmad ,  Robert Alan Bignell ,  Venkata Krishna Reddy Dumpa

IPC分类号： G06F1/32 ,  G06F9/32

CPC分类号： G06F1/3237 ,  G06F1/3206 ,  G06F9/327 ,  Y02D10/128

摘要： To preserve power and increase the overall efficiency of the CPU, the platform idle driver causes the power gate controller to cut power to the idle core. Such power gating is autonomous, i.e., the operating system and the other cores are not involved. In operation, the platform idle driver first prepares the core and the power gate controller for power gating the core. The platform idle driver then triggers the power gating. The power gate controller monitors interrupts released by the interrupt controller, and if any on the released interrupts are associated with the power gated core, the power gate controller resumes dispersing power to the core.

摘要翻译： 为了保持功率并提高CPU的整体效率，平台空闲驱动器使电源门控制器切断到空闲核心的电源。 这种电源门控是自主的，即操作系统和其他核心不涉及。 在运行中，平台空闲驱动器首先准备核心和电源门控制器，用于电源门控。 平台空闲驱动程序然后触发电源门控。 电源门控制器监视中断控制器释放的中断，如果释放的中断中的任何一个与电源门控核心相关联，则电源门控制器将恢复分配给核心的电源。

公开(公告)号：US20150253821A1

公开(公告)日：2015-09-10

申请号：US14199715

申请日：2014-03-06

申请人： Dell Products, LP

发明人： John R. Palmer ,  Syed S. Ahmed ,  Jinsaku Masuyama

IPC分类号： G06F1/18 ,  H05K7/14

CPC分类号： G06F1/3287 ,  G06F1/189 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/329 ,  G06F1/3296 ,  H05K7/1492 ,  H05K7/1498 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/24

摘要： A server rack includes a management controller, a power mapping module coupled to the management controller, and a plurality of power receptacles. Each power receptacle is coupled to the power mapping module to provide an indication to the power mapping module of the power consumed by equipment that is plugged in to each power receptacle. The management controller is operable to determine that the power consumed by the equipment installed in the server rack is greater than a first high power threshold and throttle a first piece of equipment installed in the rack space.

摘要翻译： 服务器机架包括管理控制器，耦合到管理控制器的电力映射模块和多个电源插座。 每个电源插座被耦合到功率映射模块，以向功率映射模块提供插入到每个电源插座的设备消耗的功率的指示。 管理控制器可操作以确定安装在服务器机架中的设备消耗的功率大于第一高功率阈值并且节流安装在机架空间中的第一设备。

公开(公告)号：US09122479B2

公开(公告)日：2015-09-01

申请号：US12060356

申请日：2008-04-01

申请人： Shieh-Hsing Kuo ,  Ming-Je Li ,  Shian-Ru Lin ,  Ting-Fa Yu

发明人： Shieh-Hsing Kuo ,  Ming-Je Li ,  Shian-Ru Lin ,  Ting-Fa Yu

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3209 ,  Y02D10/128

摘要： A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.

摘要翻译： 网络处理器包括收发器电路，网络数据处理单元和时钟信号控制单元。 收发电路发送和接收网络信号，将网络信号的电压电平与阈值进行比较，输出比较结果，并在第一时钟信号下工作。 网络数据处理单元耦合到收发器电路以处理网络信号，并在与第一时钟信号不同的第二时钟信号下工作。 当电压电平小于阈值时，时钟信号控制单元禁止向网络数据处理单元提供第二时钟信号，并且当电压电平不小于时能够向网络数据处理单元提供第二时钟信号 超过阈值。 还公开了一种用于网络处理器的节能方法。

公开(公告)号：US20150220672A1

公开(公告)日：2015-08-06

申请号：US14420303

申请日：2013-08-08

申请人： Samsung Electronics Co., Ltd.

发明人： Jihwan Park

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5036 ,  G06F1/3237 ,  G06F17/10 ,  G06F17/5022 ,  G06F2217/78 ,  Y02D10/128

摘要： A method of modeling power consumption of an integrated circuit and an apparatus for supporting the same are provided. The method of modeling power consumption of an integrated circuit includes: grasping information about a clock gating enable signal of the integrated circuit; determining a modeling level using a change rate of the number of the clock enable signal; and extracting a power state according to the modeling level and the number of the clock gating enable signal and modeling power consumption in the power state. Thereby, because a power state can be defined with only the number of a clock gating enable signal, a dynamic power consumption amount can be quickly and accurately estimated.

摘要翻译： 提供了一种对集成电路的功耗进行建模的方法和用于支持集成电路的装置。 集成电路的功耗建模方法包括：掌握集成电路的时钟门控使能信号; 使用所述时钟使能信号的数量的变化率来确定建模级别; 并根据建模级别和时钟门控使能信号的数量和功率状态下的建模功耗提取电源状态。 因此，由于能够仅使用时钟门控使能信号的数量来定义功率状态，因此可以快速准确地估计动态功耗量。