公开(公告)号：US5194396A

公开(公告)日：1993-03-16

申请号：US763171

申请日：1991-09-20

申请人： Young M. Kim ,  Seong J. Kang ,  Jong S. Lyu

发明人： Young M. Kim ,  Seong J. Kang ,  Jong S. Lyu

IPC分类号： H01L21/8249 ,  H01L21/70 ,  H01L27/06

CPC分类号： H01L21/70 ,  Y10S148/009

摘要： There is disclosed a method of fabricating BiCMOS semiconductor devices. External metal lines are not used for connecting the NPN bipolar device and NMOS device, or NPN bipolar device and PMOS device. In this case, the collector and base of the bipolar device are respectively in common with the drain and source of the CMOS. The bipolar transistor is in common with the bulk region of the CMOS, so that the diffusion layer is commonly used in the NPN-PMOS pair, and the diffusion layers of the connecting part are connected together in the NPN-PMOS pair. A metal line is connected to the junction of the diffusion layers, thus decreasing the connecting area of the metal line. Hence, the integrability of the chip is increased, and the metal connection causes a reduction of the RC delay time, thus improving the operational speed.

摘要翻译： 公开了一种制造BiCMOS半导体器件的方法。 外部金属线不用于连接NPN双极器件和NMOS器件，或NPN双极器件和PMOS器件。 在这种情况下，双极器件的集电极和基极分别与CMOS的漏极和源极共同。 双极晶体管与CMOS的体区共同，使得扩散层通常用于NPN-PMOS对，并且连接部分的扩散层在NPN-PMOS对中连接在一起。 金属线连接到扩散层的结，从而减少金属线的连接面积。 因此，芯片的可集成度增加，金属连接导致RC延迟时间的减少，从而提高了操作速度。

公开(公告)号：US5171702A

公开(公告)日：1992-12-15

申请号：US785174

申请日：1991-10-29

申请人： Scott H. Prengle ,  Robert H. Eklund

发明人： Scott H. Prengle ,  Robert H. Eklund

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

摘要： A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors. Subsequent patterning and etching of the polysilicon, followed by sidewall filament formation and source/drain doping, is performed to complete the structure.

摘要翻译： 公开了BiCMOS结构及其制造方法，其中发射电极和基极区之间的电介质层由沉积的电介质形成。 在双极和MOS沟槽区域的定义之后，在其上沉积多晶硅层，并从双极区域去除。 基底植入物在蚀刻多晶硅层之前或之后进行。 在其上形成一层TEOS氧化物，并被蚀刻以保留在双极区域的一部分中，其中形成了发射极接触，并且暴露出形成外部基极的双极区域的一部分。 本发明的替代实施例包括通过在其中形成侧壁氧化物长丝来缩放发射极接触。 第二层多晶硅设置在其上以形成发射电极，并与第一层合并形成MOS晶体管的栅极。 随后进行多晶硅的图案化和蚀刻，随后进行侧壁细丝形成和源极/漏极掺杂，以完成该结构。

公开(公告)号：US5141881A

公开(公告)日：1992-08-25

申请号：US510469

申请日：1990-04-18

申请人： Kazuo Takeda ,  Toshimasa Sadakata ,  Teruo Tabata ,  Nobuyuki Sekikawa ,  Tadayoshi Takada ,  Yasuhiro Tamada ,  Yoshiaki Sano

发明人： Kazuo Takeda ,  Toshimasa Sadakata ,  Teruo Tabata ,  Nobuyuki Sekikawa ,  Tadayoshi Takada ,  Yasuhiro Tamada ,  Yoshiaki Sano

IPC分类号： H01L21/761 ,  H01L21/8222

CPC分类号： H01L21/761 ,  H01L21/8222 ,  Y10S148/009 ,  Y10S148/01

摘要： A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment. The method has advantages that the upper isolating region can be prepared by heat-treatment for relatively short time, reducing lateral diffusion and the occupied area thereof, and slippage by masking is remarkably reduced, providing a semiconductor integrated circuit with high density.

公开(公告)号：US5114868A

公开(公告)日：1992-05-19

申请号：US561191

申请日：1990-08-01

申请人： Hiroshi Yoshida

发明人： Hiroshi Yoshida

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08

CPC分类号： H01L21/76218 ,  H01L21/823892 ,  Y10S148/009

摘要： First, N-type channel stoppers are formed in an element formation region of a P-channel MOS transistor and in an element isolation region of the P-channel MOS transistor, of a CMOS transistor. After forming a field oxide film, an N well is formed in the element formation region of the P-channel MOS transistor. In spite of the fact that the dose of ions used for the formation of an N-type channel stopper is smaller than the dose of ions used for the formation of an N well, the surface concentration of the N-type impurity of the N-type channel stopper is higher than that of the N well. The N-type impurity concentration in the portion where the N-type channel stopper and the N well are brought into contact, becomes uniform. The variability in the threshold voltage of the P-channel MOS transistor, the threshold voltage of the P-channel parasitic MOS transistor, the junction breakdown voltage of the P.sup.+ diffused layer and the junction capacitance of the P.sup.+ diffused layer is reduced, so that the device obtained is suited for the submicron process.

摘要翻译： 首先，在CMOS晶体管的P沟道MOS晶体管的元件形成区域和P沟道MOS晶体管的元件隔离区域中形成N型沟道截止器。 在形成场氧化膜之后，在P沟道MOS晶体管的元件形成区域中形成N阱。 尽管用于形成N型通道阻塞物的离子的剂量小于用于形成N阱的离子的剂量，但N型杂质的表面浓度， 型通道塞子比N孔高。 使N型槽塞和N阱接触的部分的N型杂质浓度变得均匀。 P沟道MOS晶体管的阈值电压的变化，P沟道寄生MOS晶体管的阈值电压，P +扩散层的结击穿电压和P +扩散层的结电容减小，使得 获得的器件适用于亚微米工艺。

公开(公告)号：US5091321A

公开(公告)日：1992-02-25

申请号：US733919

申请日：1991-07-22

申请人： Wing K. Huie ,  Alexander H. Owens

发明人： Wing K. Huie ,  Alexander H. Owens

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/10

CPC分类号： H01L29/66272 ,  H01L21/28512 ,  H01L21/8249 ,  H01L29/1004 ,  Y10S148/009 ,  Y10S148/011 ,  Y10S438/919

摘要： A vertical NPN transistor is fabricated in a silicon integrated circuit substrate growing an N-type epitaxial layer, forming a preliminary P-type base region in the surface of the epitaxial layer, covering the surface with a protective glass layer, selectively etching a hole in the glass layer at an emitter-designated place over the preliminary base region, depositing N-type impurities through the hole into the silicon surface to become the emitter, implanting P-type impurities, of a kind that diffuse faster than the N-type impurities, through the hole into the epitaxial layer and heating to at least anneal the substrate. The hole is then filled to provide electrical contact to the emitter.

摘要翻译： 在形成N型外延层的硅集成电路基板中制造垂直NPN晶体管，在外延层的表面形成预备的P型基极区域，用保护性玻璃层覆盖表面，选择性地蚀刻在 位于初始碱基区域的发射极指定位置处的玻璃层，通过孔将N型杂质沉积到硅表面中成为发射体，注入比N型杂质更快扩散的P型杂质 ，通过孔进入外延层并加热至少使基板退火。 然后填充孔以向发射器提供电接触。

公开(公告)号：US5079177A

公开(公告)日：1992-01-07

申请号：US409545

申请日：1989-09-19

申请人： Craig S. Lage ,  James E. Small ,  Bamdad Bastani

发明人： Craig S. Lage ,  James E. Small ,  Bamdad Bastani

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10

CPC分类号： H01L28/20 ,  H01L21/033 ,  H01L21/74 ,  H01L21/8249 ,  Y10S148/009

摘要： A method of making complementary vertical bipolar transistors and complementary field effect transistors on the same substrate is described. The process includes forming buried layers in a semiconductor substrate which are spaced apart in a self-aligned manner by use of a lateral etching technique to undercut the mask used for definition of the buried layers. In the process, the collector and base contacts of the bipolar devices and the corresponding conductivity-type sources and drains of the field effect transistors are combined to minimize processing steps. The process also includes a silicided polycrystalline silicon layer used to form resistors and contact the various transistors.

公开(公告)号：US5066602A

公开(公告)日：1991-11-19

申请号：US295380

申请日：1989-01-10

申请人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Tsutomu Fujita

发明人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Tsutomu Fujita

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L27/092

CPC分类号： H01L27/0244 ,  H01L21/74 ,  H01L21/761 ,  H01L21/82285 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/0922 ,  Y10S148/009 ,  Y10S148/151

摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

公开(公告)号：US5006476A

公开(公告)日：1991-04-09

申请号：US440456

申请日：1989-11-20

申请人： Jan L. De Jong ,  Jacob G. DeGroot

发明人： Jan L. De Jong ,  Jacob G. DeGroot

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8248 ,  H01L21/8249 ,  H01L29/10

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8248 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/6659 ,  Y10S148/009 ,  Y10S148/124

摘要： In a transistor fabrication process, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run. Insulating spacers (52A) are employed in forming a self-aligned base contact zone (58B). A shallow emitter (46) is created by outdiffusion from a patterned non-monocrystalline semiconductor layer (38A) that serves as the emitter contact. The fabrication process is compatible with the largely simultaneous manufacture of an insulated-gate field-effect transistor of the lightly doped drain type.

摘要翻译： 在晶体管制造工艺中，使用三步基极掺杂技术可以使垂直双极晶体管的特性在从运行到运行的高度最佳值下被可控地再现。 绝缘垫片（52A）用于形成自对准的底部接触区域（58B）。 通过从用作发射极接触的图案化非单晶半导体层（38A）向外扩散产生浅发射极（46）。 该制造工艺与大部分同时制造轻掺杂漏极型绝缘栅场效应晶体管兼容。

公开(公告)号：US4950616A

公开(公告)日：1990-08-21

申请号：US353105

申请日：1989-05-17

申请人： Chang-Won Kahng ,  Sung-Ki Min ,  Jong-Mil Youn

发明人： Chang-Won Kahng ,  Sung-Ki Min ,  Jong-Mil Youn

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/68 ,  H01L29/70

CPC分类号： H01L21/763 ,  Y10S148/009

摘要： This invention provides a method for fabricating a semiconductor device comprising the steps of forming buried layers on the silicon substrate; etching an epitaxial layer after said layer is grown up, the step further including the processes of etching selectively the silicon epitaxial layer of well region on which a high speed bipolar transistor is formed to be thin and keeping the silicon epitaxial layer of well region on which nMOS transistor is formed remained the same thickness as grown up; and forming a pMOS transistor, a nMOS transistor and a bipolar transistor. High efficiency and high integration is easily attained in fabricating the high speed bipolar transistor and high performance CMOS transistor on same chip and by reducing the difficulty in processing according to the method of present invention.

摘要翻译： 本发明提供一种制造半导体器件的方法，包括以下步骤：在硅衬底上形成掩埋层; 在所述层生长之后蚀刻外延层，该步骤还包括选择性地蚀刻其上形成有高速双极晶体管的阱区的硅外延层的工艺，并保持其上的阱区的硅外延层 形成的nMOS晶体管的长度保持相同的厚度; 以及形成pMOS晶体管，nMOS晶体管和双极晶体管。 在同一芯片上制造高速双极晶体管和高性能CMOS晶体管并且通过降低根据本发明的方法的处理难度，容易实现高效率和高集成度。

公开(公告)号：US4874717A

公开(公告)日：1989-10-17

申请号：US265948

申请日：1988-11-02

申请人： Franz Neppl ,  Ulrich Schwabe

发明人： Franz Neppl ,  Ulrich Schwabe

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/45 ,  H01L29/49 ,  H01L29/73 ,  H01L21/265

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/456 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/01

摘要： Integrated semiconductor circuits with at least one bipolar transistor (17) and at least one MOS field effect transistor (18) on a chip wherein contacts from a metal interconnect level to diffused active emitter (8) and collector (5) regions of the bipolar transistor (17) as well as the gate electrode (9) of the MOS transistor are composed of a high melting point silicide, such as tantalum, tungsten, molybenum or titanium silicide, are disclosed, along with a method of producing such circuits. In addtion to achieving independence from a metallization grid and achieving low-resistance wiring, the use of the silicide, in conjunction with the high temperature stability of silicides, enables its simultaneous use as an implantation mask. The invention allows the production of bipolar/MOS components on a chip without added outlay.

摘要翻译： 具有至少一个双极晶体管（17）和芯片上的至少一个MOS场效应晶体管（18）的集成半导体电路，其中从金属互连电平到双极晶体管的扩散有源发射极（8）和集电极（5）区域的接触 （17）以及MOS晶体管的栅极（9）以及诸如钽，钨，钼或硅化钛之类的高熔点硅化物，以及制造这种电路的方法。 除了实现与金属化电网的独立性和实现低电阻布线之外，硅化物与硅化物的高温稳定性的结合使得能够同时用作注入掩模。 本发明允许在芯片上生产双极/ MOS部件而不增加额外的费用。