公开(公告)号：US5045492A

公开(公告)日：1991-09-03

申请号：US411785

申请日：1989-09-25

申请人： Wing K. Huie ,  Alexander H. Owens ,  David S. Pan

发明人： Wing K. Huie ,  Alexander H. Owens ,  David S. Pan

IPC分类号： H01L21/76 ,  H01L21/761 ,  H01L21/8234 ,  H01L21/8249

CPC分类号： H01L21/761 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8249 ,  Y10S148/086

摘要： A method for making an integrated circuit includes forming patches of a silicon nitride mask over the areas where a high-current vertical DMOS and/or NPN transistor, where a vertical NPN transistor and where the NMOS and PMOS transistors of a CMOS pair are to be formed. The nitride mask also includes patches over a network of P-type isolation walls, and two special patches over two special areas at which N+ plugs for the DMOS and NPN transistors are to be formed. A heavy field oxide is grown everywhere except at the nitride patches. The two special patches are selectively removed and by heating and diffusing phosphorous from a POCl.sub.3 source from 950.degree. C. to 1100.degree. C. for at least 30 minutes, two very high conductivity N+ phosphorous plugs are formed through the epitaxial layer at a concentration of over 10.sup.20 phosphorous atoms/cm.sup.3, while the nitride serves to prevent the sensitive channel regions of the DMOS and CMOS transistors from phosphorous doping. This results in close self-alignment of the N+ plugs and their associated DMOS and NPN transistors leading to low on-resistance, to higher IC component density, to a high throughput rate at manufacturing and low cost.

摘要翻译： 制造集成电路的方法包括在高电流垂直DMOS和/或NPN晶体管的区域上形成氮化硅掩模的贴片，其中垂直NPN晶体管和CMOS对的NMOS和PMOS晶体管将成为 形成。 氮化物掩模还包括在P型隔离壁的网络上的贴片，以及两个特殊区域，其中将形成用于DMOS和NPN晶体管的N +插头的两个特殊区域。 除了在氮化物贴片之外，重金属氧化物生长在任何地方。 通过选择性地去除两个特殊的贴片并通过将POCl 3源中的磷从950℃加热并扩散至1100℃至少30分钟，将两个非常高的导电性N +磷塞通过外延层形成，浓度为 超过1020个磷原子/ cm3，而氮化物用于防止DMOS和CMOS晶体管的敏感通道区域进行磷掺杂。 这导致N +插头及其相关的DMOS和NPN晶体管的紧密自对准导致低导通电阻，更高的IC组件密度，在制造时成本高，成本低。

公开(公告)号：US4590665A

公开(公告)日：1986-05-27

申请号：US680199

申请日：1984-12-10

申请人： Alexander H. Owens ,  Mark A. Halfacre ,  Wing K. Huie ,  David S. Pan

发明人： Alexander H. Owens ,  Mark A. Halfacre ,  Wing K. Huie ,  David S. Pan

IPC分类号： H01L21/22 ,  H01L21/225 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/78 ,  G11C11/40

CPC分类号： H01L27/11526 ,  H01L21/22 ,  H01L21/2253 ,  H01L21/823814 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/7886 ,  Y10S148/082

摘要： A CMOS EPROM or the like is made wherein the basic memory device or EPROM device is an N-channel IGFET (insulated gate field effect transistor) having a control gate self-aligned with an underlying floating gate. The sources and drains of the EPROM devices as well as the sources and drains of peripheral N-channel transistors, are made by implanting with arsenic and with phosphorous. When heated, the faster diffusing phosphorous outruns, and extends from the bulk of, the arsenic so that these sources and drains extend slightly under the adjacent gate. This extension of the drain in the memory device enables a faster programming capability. A similar but oppositely directed lateral extension of all these sources and drains reduces the leakage to the substrate and reduces the chances of shorts to the substrate due to slightly misaligned metal to source and drain contacts.

摘要翻译： 制造CMOS EPROM等，其中基本存储器件或EPROM器件是具有与底层浮置栅极自对准的控制栅极的N沟道IGFET（绝缘栅场效应晶体管）。 EPROM器件的源极和漏极以及外围N沟道晶体管的源极和漏极通过用砷和磷进行注入而制成。 当加热时，较快的扩散磷超出，并从砷的大部分延伸，使得这些源和漏极在相邻栅极下方稍微延伸。 存储器件中漏极的这种扩展使得能够实现更快的编程能力。 所有这些源和漏极的类似但相反导向的横向延伸减少了衬底的泄漏，并且由于稍微不对准金属到源极和漏极接触而减小了衬底短路的机会。

公开(公告)号：US4914051A

公开(公告)日：1990-04-03

申请号：US281593

申请日：1988-12-09

申请人： Wing K. Huie ,  Alexander H. Owens ,  David S. Pan ,  Michael J. Zunino

发明人： Wing K. Huie ,  Alexander H. Owens ,  David S. Pan ,  Michael J. Zunino

IPC分类号： H01L21/28 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/06

CPC分类号： H01L29/66712 ,  H01L21/28 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7302 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/0696 ,  Y10S148/126

摘要： A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.

摘要翻译： 硅集成电路通过包括在DMOS晶体管和NPN晶体管中的基极区域中同时形成多个D阱区域的方法，在单独的外延阱中包括垂直功率DMOS晶体管和垂直NPN晶体管，并且包括同时形成 元素源极区域和发射极区域。 分别在DMOS和NPN晶体管中同时提供N型掩埋层。 同时形成两个分别将两个掩埋层连接到集成电路管芯的外延表面的N +插头。 这些经济上有吸引力的同步步骤都不需要任何装置的偏差与最佳几何形状。 还公开了用于形成小信号CMOS晶体管的兼容和集成步骤。 该方法还包括DMOS晶体管以及CMOS晶体管中的栅极，源极和沟道区域的完全自对准。

公开(公告)号：US5091321A

公开(公告)日：1992-02-25

申请号：US733919

申请日：1991-07-22

申请人： Wing K. Huie ,  Alexander H. Owens

发明人： Wing K. Huie ,  Alexander H. Owens

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/10

CPC分类号： H01L29/66272 ,  H01L21/28512 ,  H01L21/8249 ,  H01L29/1004 ,  Y10S148/009 ,  Y10S148/011 ,  Y10S438/919

摘要： A vertical NPN transistor is fabricated in a silicon integrated circuit substrate growing an N-type epitaxial layer, forming a preliminary P-type base region in the surface of the epitaxial layer, covering the surface with a protective glass layer, selectively etching a hole in the glass layer at an emitter-designated place over the preliminary base region, depositing N-type impurities through the hole into the silicon surface to become the emitter, implanting P-type impurities, of a kind that diffuse faster than the N-type impurities, through the hole into the epitaxial layer and heating to at least anneal the substrate. The hole is then filled to provide electrical contact to the emitter.

摘要翻译： 在形成N型外延层的硅集成电路基板中制造垂直NPN晶体管，在外延层的表面形成预备的P型基极区域，用保护性玻璃层覆盖表面，选择性地蚀刻在 位于初始碱基区域的发射极指定位置处的玻璃层，通过孔将N型杂质沉积到硅表面中成为发射体，注入比N型杂质更快扩散的P型杂质 ，通过孔进入外延层并加热至少使基板退火。 然后填充孔以向发射器提供电接触。

公开(公告)号：US07795126B2

公开(公告)日：2010-09-14

申请号：US11969756

申请日：2008-01-04

申请人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

发明人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L27/14618 ,  H01L23/482 ,  H01L23/4827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

摘要翻译： 本发明的半导体器件包括形成在具有第一和第二表面的半导体衬底上的集成电路和沿着边缘的切口区域。 第一表面包括与集成电路电连接的电接触垫。 半导体衬底的第一表面包括具有延伸超过半导体衬底的边缘的表面部分的顶部保护层。 半导体衬底的第二表面包括具有电连接器的底部保护层。 顶部保护层的表面部分包括与电接触焊盘延伸部电互连的电接触焊盘。 电接触焊盘延伸部经由背面电连接器与电连接器互连，后侧电连接器与形成搭接连接的电接触垫延伸部重叠。 还公开了用于构造这种装置和连接的方法。

公开(公告)号：US5998280A

公开(公告)日：1999-12-07

申请号：US45226

申请日：1998-03-20

申请人： Albert Bergemont ,  Alexander H. Owens

发明人： Albert Bergemont ,  Alexander H. Owens

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/7621 ,  Y10S148/05

摘要： A trench is etched in a silicon substrate covered with an oxide/nitride stack and a field oxide layer is then grown through oxidation of the silicon in the substrate such that the trench is partly filled. There is reduced oxide encroachment into the active areas under the nitride layer because of the partial field oxide growth. Double oxide layers are deposited over the surface of the field oxide layer and the oxide/nitride stack such that the oxide layers fill the remainder of the trench and produce a nearly planar topology. The double oxide layers are then etched back to the nitride layer through chemical mechanical polishing, leaving the field isolation region. After stripping the oxide/nitride stack, a gate oxide layer is grown. A minimal amount of oxide is required to fill the trench because the trench is already almost filled with the field oxide layer and because of the shallow depth of the trench. Consequently, the etch back step causes minimal dishing. Further, the field oxide layer rounds the corner between the trench and the active area, obviating the need for a thin oxide liner in the trench.

摘要翻译： 在被氧化物/氮化物堆叠覆盖的硅衬底中蚀刻沟槽，然后通过衬底中的硅的氧化生长场氧化物层，使得沟槽被部分填充。 由于部分场氧化物生长，氧化物侵蚀减少到氮化物层下面的有源区域中。 双氧化层沉积在场氧化物层和氧化物/氮化物堆叠的表面上，使得氧化物层填充沟槽的其余部分并产生几乎平面的拓扑结构。 然后通过化学机械抛光将双重氧化物层蚀刻回氮化物层，留下场隔离区域。 在剥离氧化物/氮化物堆叠之后，生长栅极氧化物层。 需要最少量的氧化物来填充沟槽，因为沟槽已经几乎被场氧化物层填充，并且由于沟槽的浅深度。 因此，回蚀步骤导致最小的凹陷。 此外，场氧化物层围绕沟槽和有源区域之间的角落，避免了在沟槽中的薄氧化物衬垫的需要。

公开(公告)号：US06579777B1

公开(公告)日：2003-06-17

申请号：US08587417

申请日：1996-01-16

申请人： Ting P. Yen ,  Pamela S. Trammel ,  Philippe Schoenborn ,  Alexander H. Owens

发明人： Ting P. Yen ,  Pamela S. Trammel ,  Philippe Schoenborn ,  Alexander H. Owens

IPC分类号： H01L2176

CPC分类号： H01L21/7621

摘要： A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

摘要翻译： 一种通过在硅衬底中设置开口的方式形成局部氧化的方法，所述局部氧化具有缩小的鸟嘴刺入半导体器件中，所述开口具有从所述凹部开口的垂直轴线测量的具有约10°至约75°之间的锥度的倾斜侧壁， 然后在锥形凹槽开口内生长场氧化物以形成局部氧化。

公开(公告)号：US5612552A

公开(公告)日：1997-03-18

申请号：US408035

申请日：1995-03-21

申请人： Alexander H. Owens

发明人： Alexander H. Owens

IPC分类号： H01L27/06 ,  H01L27/118 ,  H01L27/10 ,  H01L27/01 ,  H01L29/04 ,  H01L29/76

CPC分类号： H01L27/0688 ,  H01L27/11807

摘要： A multilevel gate array MOS-type integrated circuit structure is described wherein each source, drain, and gate electrode region in the integrated circuit structure is accessible directly through a contact opening formed normal to the plane of the underlying substrate through an overlying insulation layer. The multilevel gate array MOS-type integrated circuit structure of the invention comprises a substrate; a first semiconductor device level comprising one or more first source regions, one or more first drain regions, and one or more first gate electrode regions; and a second semiconductor device level formed over the first semiconductor device level and comprising one or more second source regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying first source region in the first level, one or more second drain regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying drain region in the first level, and one or more second gate electrode regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying gate electrode region in the first level; whereby contact openings may be formed, normal to the plane of the substrate, to each of the source, drain, and gate electrode regions in both semiconductor device levels.

摘要翻译： 描述了一种多电平栅极阵列MOS型集成电路结构，其中集成电路结构中的每个源极，漏极和栅极电极区域通过穿过覆盖的绝缘层垂直于下面的衬底的平面形成的接触开口直接访问。 本发明的多级门阵列MOS型集成电路结构包括：基板; 第一半导体器件级，包括一个或多个第一源极区，一个或多个第一漏极区和一个或多个第一栅电极区; 以及形成在第一半导体器件级上的第二半导体器件电平，并且包括一个或多个第二源极区域，第二源极区域布置成允许垂直于下面的衬底的平面到达第一电平的下面的第一源极区域，一个或多个第二 漏极区域被布置成允许垂直于下面的衬底的平面到达第一级的下面的漏极区域，以及一个或多个第二栅电极区域，被布置成允许垂直于下面的衬底的平面与 第一级的底栅极电极区域; 从而可以在垂直于衬底的平面的两个半导体器件级中的每个源极，漏极和栅电极区域上形成接触开口。

公开(公告)号：US5220192A

公开(公告)日：1993-06-15

申请号：US911861

申请日：1992-07-10

申请人： Alexander H. Owens ,  Mike Lyu ,  Shahin Toutounchi ,  Abraham Yee

发明人： Alexander H. Owens ,  Mike Lyu ,  Shahin Toutounchi ,  Abraham Yee

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L27/092 ,  H01L21/76218 ,  Y10S257/921 ,  Y10S438/953

摘要： A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.

公开(公告)号：US06946706B1

公开(公告)日：2005-09-20

申请号：US10616381

申请日：2003-07-09

申请人： Douglas Brisbin ,  David Tsuei ,  Alexander H. Owens ,  Andy Strachan

发明人： Douglas Brisbin ,  David Tsuei ,  Alexander H. Owens ,  Andy Strachan

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/4238

摘要： An LDMOS structure which provides for reduced hot carrier effects. The reduction in hot carrier effects is achieved by increasing the size of the drain region of the LDMOS relative to the size of the source region. The larger size of the drain region reduces the concentration of electrons entering the drain region. This reduction in the concentration of electrons reduces the number of impact ionizations, which in turn reduces the hot carrier effects. The overall performance of the LDMOS is improved by reducing the hot carrier effects.

摘要翻译： 提供减少热载体效应的LDMOS结构。 通过增加LDMOS的漏极区域相对于源极区域的尺寸来实现热载流子效应的降低。 漏极区域的较大尺寸减小了进入漏极区域的电子的浓度。 电子浓度的这种降低减少了冲击电离的数量，这又降低了热载流子的影响。 通过减少热载体效应，提高了LDMOS的整体性能。