公开(公告)号：US20040084692A1

公开(公告)日：2004-05-06

申请号：US10283705

申请日：2002-10-30

Inventor： Tak Hung Ning

IPC: H01L031/0328 ,  H01L031/0336 ,  H01L031/072 ,  H01L031/109

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/66318 ,  H01L29/7371 ,  H01L29/7378

Abstract: A bipolar transistor structure and process technology is described incorporating a emitter, a base, and a collector, with most of the intrinsic base adjacent the collector having a graded energy bandgap and a layer of the intrinsic base adjacent the emitter having a substantially constant energy bandgap. The invention has a smaller base transit time than a conventional graded-base-bandgap bipolar transistor.

Abstract translation: 描述了双极晶体管结构和工艺技术，其结合了发射极，基极和集电极，其中与集电极相邻的大部分本征基极具有梯度能带隙和邻近发射极的本征基极层具有基本恒定的能带隙 。 本发明具有比传统的梯度基带隙双极晶体管更小的基极传输时间。

公开(公告)号：US20040084691A1

公开(公告)日：2004-05-06

申请号：US10697589

申请日：2003-10-30

Inventor： Yong Chen ,  R. Stanley Williams

IPC: H01L031/0328 ,  H01L029/94 ,  H01L031/113 ,  H01L029/76

CPC classification number: H01L21/3081 ,  B82Y10/00 ,  G11C2213/81 ,  H01L21/3083 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42312 ,  H01L29/66439 ,  Y10S438/945 ,  Y10S438/962 ,  Y10S977/888

Abstract: A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

Abstract translation: 一种用于形成第一组合物的第一和第二线性结构的方法，所述第一和第二线性结构垂直相交，在所述结构相交点处存在间隙。 线性结构构造在具有第一组成的可蚀刻晶体层上。 在该层上生长第二组合物的第一和第二自对准纳米线，并用作蚀刻该层的掩模。 自对准纳米线由相对于晶体层具有不对称晶格失配的材料构成。 该间隙足够小以允许一个结构用作晶体管的栅极，而另一个则形成晶体管的源极和漏极。 间隙可以用电可切换材料填充，从而将晶体管转换成存储单元。

公开(公告)号：US20040075108A1

公开(公告)日：2004-04-22

申请号：US10681146

申请日：2003-10-09

Inventor： Shinichi Sonetaka ,  Yasuyuki Toyoda ,  Kazuhiro Arai ,  Yorito Ota

IPC: H01L031/0328 ,  H01L031/0336 ,  H01L031/072 ,  H01L031/109

CPC classification number: H01L29/732 ,  H01L27/0825 ,  H01L29/0692

Abstract: A bipolar transistor includes the first group of transistors 610a, the second group of transistors 610b, the third group of transistors 610c and the fourth group of transistors 610d. The groups of transistors have unit transistors with emitters, bases and collectors that are connected electrically in parallel and the number of unit transistors is different from group to group and 2, 4, 8, and 16, respectively.

Abstract translation: 双极晶体管包括第一组晶体管610a，第二组晶体管610b，第三组晶体管610c和第四晶体管组610d。 这些晶体管组具有发射极，基极和集电极的单元晶体管，它们并联电连接，单元晶体管的数量分别与组与组不同，分别为2,4,8和16。

公开(公告)号：US20040070003A1

公开(公告)日：2004-04-15

申请号：US10676963

申请日：2003-10-01

Inventor： Remigijus Gaska ,  Xuhong Hu ,  Michael Shur

IPC: H01L033/00 ,  H01L031/0328

CPC classification number: H01L33/32 ,  H01L29/2003 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/802

Abstract: A semiconductor structure having a textured nitride-based layer. The textured nitride-based layer can be formed above one or more crystalline nitride layers and a substrate, and can be formed into any desired pattern. The semiconductor structure can be incorporated as part of, for example, a field effect transistor, a light emitting diode, or a laser.

Abstract translation: 具有织构化的氮化物基层的半导体结构。 纹理氮化物基层可以形成在一个或多个结晶氮化物层和基底之上，并且可以形成任何期望的图案。 半导体结构可以作为例如场效应晶体管，发光二极管或激光器的一部分被并入。

公开(公告)号：US20040056275A1

公开(公告)日：2004-03-25

申请号：US10606660

申请日：2003-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Bruno Murari ,  Ubaldo Mastromatteo ,  Paolo Ferrari

IPC: H01L031/0328

CPC classification number: G02B27/0994

Abstract: A micromachined device made of semiconductor material is formed by: a semiconductor body; an intermediate layer set on top of the semiconductor body; and a substrate, set on top of the intermediate layer. A cavity extends in the intermediate layer and is delimited laterally by bottom fixed regions, at the top by the substrate, and at the bottom by the semiconductor body. The bottom fixed regions form fixed electrodes, which extend in the intermediate layer towards the inside of the cavity. An oscillating element is formed in the substrate above the cavity and is separated from top fixed regions through trenches, which extend throughout the thickness of the substrate. The oscillating element is formed by an oscillating platform set above the cavity, and by mobile electrodes, which extend towards the top fixed regions in a staggered way with respect to the fixed electrodes. The fixed electrodes and mobile electrodes are thus comb-fingered in plan view but formed on different levels.

Abstract translation: 由半导体材料制成的微机械加工装置由半导体本体形成， 设置在半导体本体顶部的中间层; 以及设置在中间层顶部的基板。 空腔在中间层中延伸并且由底部固定区域在顶部限定，在顶部由衬底限定，并且在底部由半导体本体限定。 底部固定区域形成固定电极，其在中间层中延伸到空腔的内部。 振荡元件形成在空腔上方的衬底中，并且通过沟槽与顶部固定区域分离，其延伸贯穿衬底的厚度。 振荡元件由设置在空腔上方的振荡平台和通过相对于固定电极以交错方式朝着顶部固定区域延伸的移动电极形成。 因此，固定电极和移动电极在平面图中梳理，但形成在不同的水平上。

公开(公告)号：US20040056273A1

公开(公告)日：2004-03-25

申请号：US10602982

申请日：2003-06-24

Applicant: Cermet, Inc.

Inventor： Jeff Nause ,  Shanthi Ganesan

IPC: H01L031/0328

CPC classification number: H01L29/22 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7786

Abstract: A zinc oxide (ZnO) field effect transistor exhibits large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially n laminated on a substrate. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type ZnO. The gate insulating film is made from aluminum nitride/aluminum gallium nitride (AlN/AlGaN) or magnesium zinc oxide (MgZnO), which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a silicon metal oxide semiconductor field effect transistor (Si-MOS-type FET), resulting in the formation of an inversion layer.

Abstract translation: 氧化锌（ZnO）场效应晶体管通过使用栅极绝缘膜表现出大的输入振幅。 沟道层和栅极绝缘膜依次层叠在基板上。 在栅极绝缘膜上形成栅电极。 源电极和漏极设置在栅电极的两侧，并且经由开口电连接到沟道层。 沟道层由n型ZnO形成。 栅极绝缘膜由氮化铝/氮化铝铝（AlN / AlGaN）或氧化镁锌（MgZnO）制成，其表现出优异的绝缘特性，从而增加肖特基势垒并实现大的输入幅度。 如果FET以增强模式工作，则其可以以类似于硅金属氧化物半导体场效应晶体管（Si-MOS型FET）的方式工作，导致反型层的形成。

公开(公告)号：US20040051117A1

公开(公告)日：2004-03-18

申请号：US10600039

申请日：2003-06-20

Inventor： Oliver Chyan ,  Thomas Ponnuswamy

IPC: H01L031/0328

CPC classification number: H01L21/76843 ,  H01L21/76864 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention generally relates to methods used for fabricating integrated circuits (nullICsnull), using Ruthenium (nullRunull) and its oxides and/or Iridium (nullIrnull) and its oxides as the diffusion barrier to contain and control copper (nullCunull) interconnects. The invention also covers ICs incorporating such materials in the diffusion barrier to contain and control the Cu interconnects. The present invention advantageously provides better integration and fabrication of advanced IC chips with sub-micron features.

Abstract translation: 本发明一般涉及使用钌（“Ru”）及其氧化物和/或铱（“Ir”）及其氧化物作为扩散屏障来制备集成电路（“IC”）的方法，以包含和控制铜（ “Cu”）互连。 本发明还包括将这种材料结合在扩散阻挡层中以包含和控制Cu互连的IC。 本发明有利地提供具有亚微米特征的先进IC芯片的更好的集成和制造。

公开(公告)号：US20040046183A1

公开(公告)日：2004-03-11

申请号：US10657529

申请日：2003-09-08

Inventor： Amitava Chatterjee

IPC: H01L031/0328 ,  H01L031/0336

CPC classification number: H01L27/0623 ,  H01L21/8249

Abstract: A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a channel stop p-well region and emitter region which are vertically oriented within a semiconductor substrate. The resulting bipolar device is junction isolated from other circuits formed on the substrate by a p-well region.

Abstract translation: 描述了使用用于形成nMOS场效应器件和pMOS场效应器件的离子注入步骤的垂直双极晶体管。 注入步骤形成在半导体衬底内垂直定向的n阱，沟道停止p阱区和发射极区。 所得到的双极器件是通过p-阱区与在衬底上形成的其它电路隔离的结。

公开(公告)号：US20040041617A1

公开(公告)日：2004-03-04

申请号：US10233232

申请日：2002-08-30

Inventor： Gregory S. Snider ,  Philip J. Kuekes ,  R. Stanley Williams

IPC: H03K017/00 ,  H01L021/8244 ,  G11C013/00 ,  H01L025/00 ,  H03K019/177 ,  H01L031/109 ,  H01L031/072 ,  H01L031/0336 ,  H01L031/0328 ,  H01L029/06 ,  H01L021/8234 ,  G11C011/00 ,  H03K019/00 ,  H04Q001/00

CPC classification number: H01L27/285 ,  B82Y10/00 ,  G11C13/0009 ,  G11C13/0014 ,  G11C2213/14 ,  G11C2213/34 ,  G11C2213/77 ,  G11C2213/81

Abstract: A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.

Abstract translation: 用于实现具有增益的至少一个电子电路的计算系统包括至少一个二维分子开关阵列。 分子开关阵列通过将两个或更多个交叉的导线平面组装成器件的配置而形成。 每个装置包括由一对交叉线形成的连接点和连接该连接处的一对交叉线的至少一个连接器种类。 该结具有纳米的功能尺寸，并且包括由（1）一个或多个连接器种类和一对交叉导线提供的切换能力，以及（2）具有第一状态的可配置纳米级线晶体管，其具有作为 晶体管和作为导电半导体线的第二状态。 进行具体的连接来连接设备并将设备连接到提供高和低电压的两个结构。

公开(公告)号：US20040031956A1

公开(公告)日：2004-02-19

申请号：US10619228

申请日：2003-07-14

Inventor： Adam William Saxler

IPC: H01L029/06 ,  H01L031/0328

CPC classification number: H01L29/205 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0259 ,  H01L29/2003 ,  H01L33/02 ,  H01L33/025

Abstract: Semiconductor devices include a wide bandgap semiconductor layer having an array of discontinuous wide bandgap semiconductor regions therein that contribute to a reduction in ionization energies of dopants in the wide bandgap semiconductor layer relative to an otherwise equivalent wide bandgap semiconductor layer that is devoid of the array of discontinuous wide bandgap semiconductor regions. The discontinuous wide bandgap semiconductor regions and the wide bandgap semiconductor layer have the same net conductivity type, but the discontinuous wide bandgap semiconductor regions are typically more highly doped to thereby provide excess charge carriers to the wide bandgap semiconductor layer.

Abstract translation: 半导体器件包括宽带隙半导体层，其具有其中不连续的宽带隙半导体区域的阵列，其有助于降低宽带隙半导体层中的掺杂剂的电离能，相对于其它等效的宽带隙半导体层，其不具有 不连续的宽带隙半导体区域。 不连续的宽带隙半导体区域和宽带隙半导体层具有相同的净电导率类型，但是不连续的宽带隙半导体区域通常更高掺杂，从而向宽带隙半导体层提供过量的电荷载流子。