公开(公告)号：US20140049293A1

公开(公告)日：2014-02-20

申请号：US13588429

申请日：2012-08-17

申请人： Shekar Mallikarjunaswamy

发明人： Shekar Mallikarjunaswamy

IPC分类号： H03K3/353 ,  H01L21/98

CPC分类号： H01L21/8234 ,  H01L21/8221 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/66681 ,  H01L2924/0002 ,  H03K17/687 ,  H01L2924/00

摘要： A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit

摘要翻译： 三维（3D）栅极驱动器集成电路包括堆叠在低侧集成电路上的高侧集成电路，其中高侧集成电路和低侧集成电路使用贯穿硅通孔（TSV）互连， 。 如此形成的，高侧集成电路和低侧集成电路可以形成为没有端接区域而不具有掩埋层。 3D栅极驱动器集成电路提高了高压集成的便利性，并提高了栅极驱动器集成电路的坚固性和可靠性

公开(公告)号：US08508307B2

公开(公告)日：2013-08-13

申请号：US13158054

申请日：2011-06-10

申请人： Kazuhiro Mitsuda ,  Koji Okada ,  Suguru Tachibana

发明人： Kazuhiro Mitsuda ,  Koji Okada ,  Suguru Tachibana

IPC分类号： H03L1/02 ,  H03K3/26 ,  H03K3/353

CPC分类号： H03L1/04 ,  G05F3/30 ,  H03K3/011 ,  H03K3/027

摘要： An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.

摘要翻译： 一种包括参考电压产生电路的振荡电路，其将与绝对温度成比例增加的比例绝对温度（PTAT）输出添加到互补绝对温度（CTAT）输出，其降低 与绝对温度成比例，以产生和输出参考电压。 振荡电路产生具有期望和固定频率的振荡信号。

公开(公告)号：US20120086515A1

公开(公告)日：2012-04-12

申请号：US13005054

申请日：2011-01-12

申请人： Jeong Mo YANG ,  Changsik YOO ,  Young-Jin MOON ,  Yong-Seong ROH ,  Joong Ho CHOI ,  Jae Shin LEE ,  Jung Chul GONG ,  Yu Jin JANG

发明人： Jeong Mo YANG ,  Changsik YOO ,  Young-Jin MOON ,  Yong-Seong ROH ,  Joong Ho CHOI ,  Jae Shin LEE ,  Jung Chul GONG ,  Yu Jin JANG

IPC分类号： H03K3/353

CPC分类号： H03K3/354 ,  H03K3/0231 ,  H03K3/03 ,  H03K5/1534

摘要： There is provided relaxation oscillator. The relaxation oscillator includes: a ramp wave generator generating ramp waves by a complementary operation between a first capacitor module charged and discharged according to a first switching signal and a second capacitor module charged and discharged according to a second switching signal; a negative feedback circuit unit generating a compensation voltage for compensating errors with reference voltage by being fedback with the ramp waves; and a switching signal generator generating the first switching signal controlling the charging and discharging of the first capacitor module and the second switching signal controlling the charging and discharging of the second capacitor module from the compensation voltage and the ramp waves. As a result, the present invention can generate ramp waves having a stable frequency while preventing a frequency from being changed due to a delay or an offset of the comparator.

摘要翻译： 提供放松振荡器。 张弛振荡器包括：斜波发生器，通过根据第一开关信号充电和放电的第一电容器模块与根据第二开关信号充放电的第二电容器模块之间的互补操作产生斜波; 负反馈电路单元，通过与斜波反馈产生用于通过参考电压补偿误差的补偿电压; 以及切换信号发生器，其产生控制第一电容器模块的充电和放电的第一开关信号和控制第二电容器模块从补偿电压和斜波的充电和放电的第二开关信号。 结果，本发明可以产生具有稳定频率的斜坡波，同时防止频率由于比较器的延迟或偏移而改变。

公开(公告)号：US20100097135A1

公开(公告)日：2010-04-22

申请号：US12444140

申请日：2007-10-03

申请人： Gilberto Curatola ,  Prabhat Agarwal ,  Jan W. Slotboom ,  Godefridus A.M. Hurkx ,  Radu Surdeanu

发明人： Gilberto Curatola ,  Prabhat Agarwal ,  Jan W. Slotboom ,  Godefridus A.M. Hurkx ,  Radu Surdeanu

IPC分类号： H03K3/353 ,  H01L29/78

CPC分类号： H01L29/161 ,  H01L29/165 ,  H01L29/7391

摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).

摘要翻译： 隧道晶体管包括与漏扩散（6）相反的导电类型的源极扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。 绝缘栅极（16）控制耗尽层的位置和厚度。 该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

公开(公告)号：US06933760B2

公开(公告)日：2005-08-23

申请号：US10666508

申请日：2003-09-19

申请人： Nazar Syed Haider ,  Sooseok Oh

发明人： Nazar Syed Haider ,  Sooseok Oh

IPC分类号： G05F1/46 ,  H03K3/353 ,  H03K17/687

CPC分类号： G05F1/465

摘要： A voltage reference generator for a hysteresis circuit, comprising a first originator circuit to generate a first reference voltage; a second originator circuit to generate a second reference voltage; and a selector circuit, coupled to the first and second originator circuits, to select one of the first and second reference voltages to be an output reference voltage based upon an input signal to the hysteresis circuit undertaking a low-to-high or a high-to-low signal transition respectively. The first originator circuit includes a first plurality of channel devices selected from either p-channel devices or n-channel devices and the second originator circuit includes a second plurality of channel devices selected from the other one of the p-channel devices and the n-channel devices.

公开(公告)号：US20050062515A1

公开(公告)日：2005-03-24

申请号：US10958568

申请日：2004-10-06

申请人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

发明人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

IPC分类号： G02F1/1345 ,  G02F1/133 ,  G02F1/1368 ,  G06F1/04 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H01L51/50 ,  H03K3/013 ,  H03K3/353 ,  H03K17/00 ,  H03K17/693 ,  H03K19/0175 ,  H03L5/00 ,  H05B33/14

CPC分类号： G11C19/28 ,  G09G3/3688 ,  G09G2310/0275 ,  G11C19/00

摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

摘要翻译： 一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。 一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。 另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为 高于（VDD + VthN）。 因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。然后，后级的输出被输入到TFT103，使TFT103导通，同时电位 的TFT102和106的节点α的下降以使TFT 105关闭。 结果，输出节点的电位变为低电平。

公开(公告)号：US5929685A

公开(公告)日：1999-07-27

申请号：US896756

申请日：1997-07-18

申请人： Ga-Pyo Nam

发明人： Ga-Pyo Nam

IPC分类号： G11C11/417 ,  G11C5/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  H03K3/037 ,  H03K3/356 ,  H03K3/353

CPC分类号： H03K3/356113 ,  H03K3/0375

摘要： A mode setting circuit for generating a mode setting signal for selecting a particular operational mode in response to an input signal from a mode setting pad. The mode setting circuit includes a driver circuit for generating a mode setting signal in response to an input voltage of a mode setting pad, a first pull-down transistor for discharging a voltage at the mode setting pad, and a second pull-down transistor for discharging the voltage at the mode setting pad in response to a signal from the driver circuit. Such mode setting circuit can prevent a misoperation which may occasionally be caused by ground noises when the mode setting pad is not coupled to the supply voltage terminal. Thus, the reliability of the manufactured goods will be increased.

摘要翻译： 一种模式设置电路，用于响应于来自模式设置垫的输入信号而产生用于选择特定操作模式的模式设置信号。 该模式设置电路包括用于响应于模式设置焊盘的输入电压产生模式设置信号的驱动器电路，用于在模式设置焊盘处放电的第一下拉晶体管和用于在模式设置焊盘处放电的第二下拉晶体管， 响应于来自驱动器电路的信号在模式设置焊盘处放电。 这种模式设置电路可以防止当模式设置垫没有耦合到电源电压端子时偶尔由于接地噪声引起的误操作。 因此，制成品的可靠性将会提高。

公开(公告)号：US5880611A

公开(公告)日：1999-03-09

申请号：US901034

申请日：1997-07-25

申请人： Eric J. Danstrom

发明人： Eric J. Danstrom

IPC分类号： H03K3/2897 ,  H03K3/0233 ,  H03K3/353 ,  H03K5/08 ,  H03K5/24 ,  H03K17/22

CPC分类号： H03K17/223 ,  H03K17/22 ,  H03K3/02337 ,  H03K5/2418 ,  H03K5/2445 ,  H03K2017/226

摘要： A comparator with a built-in offset is disclosed. The claimed comparator includes a bias current circuit, a differential input stage with the built-in of-set, and a hysteresis circuit. The built-in offset is generated by using a resistor in the differential input stage of the comparator such that the resistor is driven by the bias current as well as the current generated by the hysteresis circuit. Additionally, a reset circuit which uses the comparator with the built-in offset is claimed. The reset circuit uses a voltage divider circuit to divide a first input voltage to the comparator. A band-gap voltage reference is used to provide a second input voltage to the comparator. Therefore, the reset circuit generates a reset signal when the divided voltage reaches the value of the band-gap voltage plus the offset. In another embodiment, a comparator having a differential input stage, an output stage, and a bias circuit with a hysteresis circuit is disclosed. The hysteresis circuit selectively applies a bias voltage to the differential input stage to achieve the hysteresis.

摘要翻译： 公开了具有内置偏移的比较器。 所要求的比较器包括偏置电流电路，具有内置功能的差分输入级和滞后电路。 通过在比较器的差分输入级中使用电阻来产生内置偏移，使得电阻由偏置电流驱动，以及由滞后电路产生的电流驱动。 另外，要求使用具有内置偏移的比较器的复位电路。 复位电路使用分压电路将第一输入电压分配给比较器。 使用带隙电压基准来向比较器提供第二输入电压。 因此，当分压达到带隙电压加偏移值时，复位电路产生复位信号。 在另一实施例中，公开了具有差分输入级，输出级和具有滞后电路的偏置电路的比较器。 滞后电路选择性地将偏置电压施加到差分输入级以实现滞后。

公开(公告)号：US5796281A

公开(公告)日：1998-08-18

申请号：US681358

申请日：1996-07-23

申请人： Takanori Saeki ,  Yukio Fukuzo

发明人： Takanori Saeki ,  Yukio Fukuzo

IPC分类号： H03K3/353 ,  H03F3/343 ,  H03K3/3565 ,  H03K17/16 ,  H03K19/0175 ,  H03K19/0948 ,  H03K3/297 ,  H03K19/094

CPC分类号： H03K17/162 ,  H03K3/3565

摘要： In an interface for an input signal with a small amplitude and a high bit rate, the output voltage of a receiver can become more indeterminate when the input signal voltage at the receiving end of a signal transmission line becomes equal to a reference voltage V.sub.ref. In the input buffer circuit of the CMOS current mirror type, a transistor Q.sub.2 is connected in parallel with another transistor Q.sub.1, where the conductivity types of both the transistors are the same and a reference voltage V.sub.ref is applied to the gate electrode of the transistor Q.sub.1. The transistor Q.sub.2 endows the input buffer circuit with a hysteresis characteristic, and the output power N1 of the input buffer circuit is supplied to the gate electrode of the transistor Q.sub.2.

摘要翻译： 在具有小幅度和高比特率的输入信号的接口中，当信号传输线的接收端的输入信号电压变为等于参考电压Vref时，接收机的输出电压可能变得更加不确定。 在CMOS电流反射镜类型的输入缓冲电路中，晶体管Q2与另一个晶体管Q1并联连接，其中两个晶体管的导电类型相同，并且将参考电压Vref施加到晶体管Q1的栅电极 。 晶体管Q2赋予输入缓冲电路具有滞后特性，输入缓冲电路的输出功率N1被提供给晶体管Q2的栅电极。

公开(公告)号：US5592114A

公开(公告)日：1997-01-07

申请号：US275172

申请日：1994-07-14

申请人： Chung-Yu Wu ,  Shu-Yuan Chin

发明人： Chung-Yu Wu ,  Shu-Yuan Chin

IPC分类号： H03K19/096 ,  H03K3/353

CPC分类号： H03K19/0963

摘要： A true type single-phase shift circuit including a pair of PMOS transistors, a pair of NMOS transistors, a pair of first-type MOS transistors and one second-type transistor. The source terminals of the two PMOS transistors are both coupled to a first electric potential, the gate terminal of one PMOS transistor is coupled to a data signal, and the gate terminal of the second PMOS transistor is connected between the two first-type MOS transistors. The source terminals of the two NMOS transistors are both coupled to a second electric potential; the gate terminal of one NMOS transitors is coupled to the data signal and the gate of the second NMOS transistor is connected between the two first-type MOS transistors. The two first type MOS transistors are serially connected between the drain terminals of one of the two PMOS transistors and the drain terminal of one of the two NMOS transistors. Each gate terminal of the two first type MOS transistors is coupled to a clock pulse signal. The second-type MOS transistor is serially connected between the drain terminal of the other PMOS transistor and the drain terminal of the other NMOS transistor. The gate terminal of the second type MOS transistor is coupled with the clock pulse signal and its drain terminal is used as an output terminal.

摘要翻译： 一种真正型单相移相电路，包括一对PMOS晶体管，一对NMOS晶体管，一对第一型MOS晶体管和一个第二型晶体管。 两个PMOS晶体管的源极端子都耦合到第一电位，一个PMOS晶体管的栅极端子耦合到数据信号，并且第二PMOS晶体管的栅极端子连接在两个第一型MOS晶体管 。 两个NMOS晶体管的源极端子都耦合到第二电位; 一个NMOS运算器的栅极端子耦合到数据信号，第二NMOS晶体管的栅极连接在两个第一型MOS晶体管之间。 两个第一类型MOS晶体管串联连接在两个PMOS晶体管之一的漏极端子和两个NMOS晶体管之一的漏极端子之间。 两个第一类型MOS晶体管的每个栅极端子耦合到时钟脉冲信号。 第二型MOS晶体管串联连接在另一个PMOS晶体管的漏极端子和另一个NMOS晶体管的漏极端子之间。 第二型MOS晶体管的栅极端子与时钟脉冲信号耦合，其漏极端子用作输出端子。