公开(公告)号：US07672176B2

公开(公告)日：2010-03-02

申请号：US11948486

申请日：2007-11-30

Applicant: Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin

Inventor： Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin

IPC: G11C7/22

CPC classification number: G11C5/147 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078

Abstract: A writing circuit for a phase change memory is provided. The writing circuit comprises a driving current generating circuit, a first switch device, a first memory cell and a second switch device. The driving current generating circuit provides a writing current to the first memory cell. The first switch device is coupled to the driving current generating circuit. The first memory cell is coupled between the first switch device and the second switch device. The second switch device is coupled between the first memory cell and a ground, wherein when the driving current generating circuit outputs the writing current to the first memory cell, the second switch device is turned on after the first switch device has been turned on for a first predetermined time period.

Abstract translation: 提供了一种用于相变存储器的写入电路。 写入电路包括驱动电流产生电路，第一开关器件，第一存储器单元和第二开关器件。 驱动电流产生电路向第一存储单元提供写入电流。 第一开关器件耦合到驱动电流产生电路。 第一存储器单元耦合在第一开关器件和第二开关器件之间。 第二开关装置耦合在第一存储单元和地之间，其中当驱动电流产生电路向第一存储单元输出写入电流时，第二开关器件在第一开关器件接通之后导通， 第一预定时间段。

公开(公告)号：US20100045774A1

公开(公告)日：2010-02-25

申请号：US12545296

申请日：2009-08-21

Applicant: Mei LEN ,  Chin-Hai Chang

Inventor： Mei LEN ,  Chin-Hai Chang

IPC: H04N7/00 ,  G02B13/06

CPC classification number: G02B13/06 ,  G03B37/00 ,  H04N5/2254 ,  H04N5/2259 ,  H04N5/23238

Abstract: A panoramic camera system is disclosed that includes an unified optical system, an image capture device, and a processing unit. The unified optical system may include a first set of lenses that guide images received from horizontal directions of a target scene that surrounds the unified optical system. The unified optical system may also include a deflecting device that deflects the images guided through the first set of lenses and a second set of lenses that projects the images deflected by the deflecting device. The image capture device collects the projected images into a determined pattern based on the second set of lenses. Moreover, the processing unit processes the collected images from the image capture device to generate at least one of image signals and video signals representing a panoramic rendition of the target scene.

Abstract translation: 公开了一种全景相机系统，其包括统一的光学系统，图像捕获装置和处理单元。 统一的光学系统可以包括引导从包围统一光学系统的目标场景的水平方向接收的图像的第一组透镜。 统一的光学系统还可以包括偏转装置，该偏转装置偏转引导穿过第一组透镜的图像和投影由偏转装置偏转的图像的第二组透镜。 图像捕获装置基于第二组透镜将投影图像收集成确定的图案。 此外，处理单元处理从图像捕获装置收集的图像，以产生表示目标场景的全景再现的图像信号和视频信号中的至少一个。

公开(公告)号：US20100041192A1

公开(公告)日：2010-02-18

申请号：US12190500

申请日：2008-08-12

Applicant: Lih Wei Lin ,  Wei Sheng Hsu

Inventor： Lih Wei Lin ,  Wei Sheng Hsu

IPC: H01L21/336

CPC classification number: H01L29/66606 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66636 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for preparing a multi-level flash memory structure comprises the steps of forming a protrusion in a semiconductor substrate, forming a plurality of storage structures at the sides of the protrusion, forming a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, forming a gate structure on the dielectric layer, and forming a plurality of diffusion regions at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate.

Abstract translation: 一种制备多级闪速存储器结构的方法包括以下步骤：在半导体衬底中形成突起，在突起的侧面形成多个存储结构，形成覆盖存储结构的绝缘层和半导体的突出部 在电介质层上形成栅极结构，在突起的侧面形成多个扩散区域。 每个存储结构包括电荷捕获位点和将电荷捕获位点与半导体衬底隔离的绝缘结构。

公开(公告)号：US20100038745A1

公开(公告)日：2010-02-18

申请号：US12193502

申请日：2008-08-18

Applicant: HSIAO CHE WU ,  WEN LI TSAI

Inventor： HSIAO CHE WU ,  WEN LI TSAI

IPC: H01L23/58

CPC classification number: H01L21/76232 ,  H01L21/7624 ,  H01L21/76264 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

Abstract translation: 集成电路结构包括半导体衬底，位于半导体衬底中的器件区域，与器件区域相邻的绝缘区域，位于绝缘区域中的隔离结构，其包括瓶部分和填充有电介质材料的颈部， 以及夹在器件区域和绝缘区域之间的电介质层。

公开(公告)号：US20100022058A1

公开(公告)日：2010-01-28

申请号：US12178391

申请日：2008-07-23

Applicant: LIH WEI LIN ,  WEI SHENG HSU ,  YAN RU YANG ,  YEN WEN CHEN

Inventor： LIH WEI LIN ,  WEI SHENG HSU ,  YAN RU YANG ,  YEN WEN CHEN

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

Abstract: A method for preparing a multi-level flash memory comprising the steps of forming a recess in a semiconductor substrate, forming a plurality of storage structures at the sides of the recess, and forming a gate structure having a lower block in the recess and an upper block on the lower block. The storage structures are separated by the gate structure, and each of the storage structures includes a charge-trapping site and an insulation structure surrounding the charge-trapping site.

Abstract translation: 一种制备多级闪速存储器的方法，包括以下步骤：在半导体衬底中形成凹陷，在凹槽的侧面形成多个存储结构，并形成在凹部中具有下部块的栅极结构，以及上部 块在下块上。 存储结构由栅极结构分开，并且每个存储结构包括电荷捕获位点和围绕电荷捕获位点的绝缘结构。

公开(公告)号：US20090323433A1

公开(公告)日：2009-12-31

申请号：US12147012

申请日：2008-06-26

Applicant: LING WEN HSIAO

Inventor： LING WEN HSIAO

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

Abstract: A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the reference bit line. The data sensing method comprises the steps of turning off the transistor when the stored data is a predetermined value before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line, and turning on the transistor when the stored data is opposite to the predetermined value such that a charge sharing process occurs between the storage capacitor and a parasitic capacitor of the bit line before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line.

Abstract translation: 一种用于动态随机存取存储器的数据感测方法，包括配置为存储数据的存储电容器，位线，连接存储电容器和位线的晶体管，参考位线和连接位线和参考电压的读出放大器 位线。 数据检测方法包括以下步骤：当存储的数据是预定值时，在使读出放大器感测位线和参考位线的电压之前关断晶体管，并且当存储的数据相反时，接通晶体管 达到预定值，使得在使读出放大器感测位线和参考位线的电压之前，在存储电容器和位线的寄生电容器之间发生电荷共享处理。

公开(公告)号：US20090250691A1

公开(公告)日：2009-10-08

申请号：US12203891

申请日：2008-09-03

Applicant: Chen-Ming Huang

Inventor： Chen-Ming Huang

IPC: H01L29/18 ,  G11C11/00 ,  H01L21/06

CPC classification number: G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1691

Abstract: A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate.

Abstract translation: 提供了一种相变存储器及其制造方法。 相变存储元件包括：基板; 形成在基板上并且彼此平行的矩形电介质图案; 导电图案部分地覆盖电介质图案的第一侧壁和顶表面以及衬底，以暴露电介质图案的第一侧壁和第二侧壁，其中覆盖相同电介质图案的导电图案彼此分开; 形成在基板上并直接与电介质图案的暴露的第一和第二侧壁接触的相变间隔件，其中覆盖相同电介质图案的两个相邻导电图案通过相变间隔件电连接; 以及形成在基板上的电介质层。

公开(公告)号：US07592219B2

公开(公告)日：2009-09-22

申请号：US11624220

申请日：2007-01-18

Applicant: Tsung-De Lin ,  Cheng-Che Lee

Inventor： Tsung-De Lin ,  Cheng-Che Lee

IPC: H01L21/8242

CPC classification number: H01L28/60 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then formed on the LPCs. Thereafter, a plurality of second contacts is formed on a first portions of the first contacts and a plurality of bit lines connecting a second portions of the first contacts is formed, simultaneously. An inter-layer dielectric (ILD) layer is formed on the substrate to cover the second contacts and the bit lines. Subsequently, a plurality of capacitors is formed in the ILD layer. Thus, the fabrication of the capacitor is simplified.

Abstract translation: 提供了一种通过位线（COB）制造电容器的方法。 首先，提供基板，并在基板上形成多个字线。 接下来，在字线之间形成多个着陆插头触点（LPC），然后在LPC上形成多个第一触点。 此后，多个第二触点形成在第一触点的第一部分上，同时形成连接第一触点的第二部分的多个位线。 在衬底上形成层间介电层（ILD）层以覆盖第二接触点和位线。 随后，在ILD层中形成多个电容器。 因此，简化了电容器的制造。

公开(公告)号：US20090212794A1

公开(公告)日：2009-08-27

申请号：US12190565

申请日：2008-08-12

Applicant: Chung-I Chang ,  Hui-An Chang ,  Neng-Cheng Wang

Inventor： Chung-I Chang ,  Hui-An Chang ,  Neng-Cheng Wang

IPC: G01R31/305

CPC classification number: H01L22/34 ,  G01R31/2884 ,  G01R31/307

Abstract: A test key for a semiconductor structure is provided for in-line defecting defects of the contact. The test key is disposed on a scribe line of a wafer substrate, and includes conductive structures and contacts under test. The conductive structures are electrically connected with the substrate and the contacts under test are not electrically connected with the substrate. The conductive structures and the contacts under test are regularly arranged in array. When an electronic beam is utilized to perform in-line monitoring, the normal contacts under test will be shown as bright dots and the bright dots are regularly arranged in the array; any contact under test with defect will be shown as a dark dot which results in an irregular arrangement of the bright dots.

Abstract translation: 提供了用于半导体结构的测试键，用于接触的在线缺陷缺陷。 测试键设置在晶片衬底的划线上，并且包括测试中的导电结构和触点。 导电结构与衬底电连接，被测触点不与衬底电连接。 导电结构和被测接点是规则排列的。 当使用电子束进行在线监测时，被测试的正常接触点将显示为亮点，亮点规则排列在阵列中; 任何有缺陷的接触器都将显示为暗点，导致亮点不规则排列。

公开(公告)号：US20090147566A1

公开(公告)日：2009-06-11

申请号：US12268581

申请日：2008-11-11

Applicant: Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/75 ,  G11C2213/76 ,  G11C2213/79

Abstract: A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein.

Abstract translation: 一种相变存储器，其中几个相变存储元件串联耦合以共享单个电流源。 由电流源提供的电流由多个开关引导。 为了写入/读取相变存储元件，本发明提供了控制由当前源产生的当前值并控制开关状态的技术。 相变存储元件的阻抗求和随其中存储的数据而变化。