中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

49 records (took 0.02 seconds)

    Semiconductor test structures
    1.
    发明授权
    Semiconductor test structures 有权
    半导体测试结构

    公开(公告)号：US08704224B2

    公开(公告)日：2014-04-22

    申请号：US13241634

    申请日：2011-09-23

    Applicant: An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    Inventor： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    IPC: H01L23/10

    CPC classification number: G01R31/2644 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.

    Abstract translation: 一种电阻测试结构，其包括具有有源区的半导体衬底，形成在有源区上的栅极叠层，与栅极堆叠的相对侧上的有源区连通的第一电触点，第一电触点提供跨越 栅极堆叠的第一尺寸和与栅极堆叠的相对侧上的有源区域连通的第二电触点，第二电触点跨过栅极堆叠的第一维度提供电短路，第一和第二电极 接触件沿垂直于第一尺寸的栅极堆叠的第二尺寸间隔开。

    Self-aligned static random access memory (SRAM) on metal gate
    3.
    发明授权
    Self-aligned static random access memory (SRAM) on metal gate 有权
    金属门上的自对准静态随机存取存储器（SRAM）

    公开(公告)号：US08614131B2

    公开(公告)日：2013-12-24

    申请号：US12364701

    申请日：2009-02-03

    Applicant: An-Chun Tu ,  Chen-Ming Huang

    Inventor： An-Chun Tu ,  Chen-Ming Huang

    IPC: H01L21/336

    CPC classification number: H01L21/823475 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/66545

    Abstract: A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions.

    Abstract translation: 公开了一种制造集成电路的方法，该集成电路在减小装置尺寸的同时提供放大的接触处理窗口。 该方法包括提供包括第一区域和第二区域的衬底，所述第一和第二区域具有包括虚拟栅极层的一个或多个栅极结构; 从第一和第二区域中的一个或多个栅极结构中的至少一个去除伪栅极层，以在第一和第二区域中形成一个或多个沟槽; 用导电层填充第一和第二区域中的一个或多个沟槽; 选择性地蚀刻衬底的第二区域中的一个或多个栅极结构的导电层; 在所述第二区域中的所述一个或多个栅极结构的蚀刻背面导电层上形成保护层; 以及在所述第一和第二区域中形成一个或多个接触开口。

    Flash memory cell with split gate structure and method for forming the same
    4.
    发明授权
    Flash memory cell with split gate structure and method for forming the same 有权
    具有分离栅结构的闪存单元及其形成方法

    公开(公告)号：US07951670B2

    公开(公告)日：2011-05-31

    申请号：US11368714

    申请日：2006-03-06

    Applicant: Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

    Inventor： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

    IPC: H01L21/336

    CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    Abstract: A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

    Abstract translation: 分离门存储单元。 浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。 浮栅设置在一对隔离结构之间，并且不与其上表面重叠。 盖层设置在浮动栅上。 控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。 源极区域形成在靠近浮动栅极一侧的衬底中。

    NOVEL SELF-ALIGNED STATIC RANDOM ACCESS MEMORY (SRAM) ON METAL GATE
    5.
    发明申请
    NOVEL SELF-ALIGNED STATIC RANDOM ACCESS MEMORY (SRAM) ON METAL GATE 有权
    金属门上的新型自对准静态随机存取存储器（SRAM）

    公开(公告)号：US20100197141A1

    公开(公告)日：2010-08-05

    申请号：US12364701

    申请日：2009-02-03

    Applicant: An-Chun Tu ,  Chen-Ming Huang

    Inventor： An-Chun Tu ,  Chen-Ming Huang

    IPC: H01L21/304

    CPC classification number: H01L21/823475 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/66545

    Abstract: A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions.

    Abstract translation: 公开了一种制造集成电路的方法，该集成电路在减小装置尺寸的同时提供放大的接触处理窗口。 该方法包括提供包括第一区域和第二区域的衬底，所述第一和第二区域具有包括虚拟栅极层的一个或多个栅极结构; 从第一和第二区域中的一个或多个栅极结构中的至少一个去除伪栅极层，以在第一和第二区域中形成一个或多个沟槽; 用导电层填充第一和第二区域中的一个或多个沟槽; 选择性地蚀刻衬底的第二区域中的一个或多个栅极结构的导电层; 在所述第二区域中的所述一个或多个栅极结构的蚀刻背面导电层上形成保护层; 以及在所述第一和第二区域中形成一个或多个接触开口。

    PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FORMING THE SAME
    6.
    发明申请
    PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FORMING THE SAME 有权
    相变记忆元件及其形成方法

    公开(公告)号：US20090250691A1

    公开(公告)日：2009-10-08

    申请号：US12203891

    申请日：2008-09-03

    Applicant: Chen-Ming Huang

    Inventor： Chen-Ming Huang

    IPC: H01L29/18 ,  G11C11/00 ,  H01L21/06

    CPC classification number: G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1691

    Abstract: A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate.

    Abstract translation: 提供了一种相变存储器及其制造方法。 相变存储元件包括：基板; 形成在基板上并且彼此平行的矩形电介质图案; 导电图案部分地覆盖电介质图案的第一侧壁和顶表面以及衬底，以暴露电介质图案的第一侧壁和第二侧壁，其中覆盖相同电介质图案的导电图案彼此分开; 形成在基板上并直接与电介质图案的暴露的第一和第二侧壁接触的相变间隔件，其中覆盖相同电介质图案的两个相邻导电图案通过相变间隔件电连接; 以及形成在基板上的电介质层。

    PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME
    7.
    发明申请
    PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME 失效
    相变存储器件及其制造方法

    公开(公告)号：US20080241741A1

    公开(公告)日：2008-10-02

    申请号：US11745980

    申请日：2007-05-08

    Applicant: Chen-Ming Huang

    Inventor： Chen-Ming Huang

    IPC: G11B7/24

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer.

    Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括衬底。 介电层形成在衬底上，并且相变材料层嵌入电介质层中。 第一导电电极也嵌入电介质层中以穿透相变材料层并且垂直于电介质层的顶表面延伸。

    Split-gate memory cells and fabrication methods thereof
    8.
    发明申请
    Split-gate memory cells and fabrication methods thereof 有权
    分离栅存储单元及其制造方法

    公开(公告)号：US20080121975A1

    公开(公告)日：2008-05-29

    申请号：US11592290

    申请日：2006-11-03

    Applicant: Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    Inventor： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC: H01L29/788

    CPC classification number: H01L27/115 ,  H01L27/11521

    Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

    Abstract translation: 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Split-gate memory cells and fabrication methods thereof
    9.
    发明申请
    Split-gate memory cells and fabrication methods thereof 失效
    分离栅存储单元及其制造方法

    公开(公告)号：US20080105917A1

    公开(公告)日：2008-05-08

    申请号：US11785382

    申请日：2007-04-17

    Applicant: Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    Inventor： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC: H01L29/788 ,  H01L27/115

    CPC classification number: H01L27/115 ,  H01L27/11521

    Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

    Abstract translation: 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

Patent Agency Ranking