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    Uniform layouts for SRAM and register file bit cells
    301.
    发明授权
    Uniform layouts for SRAM and register file bit cells 有权

    公开(公告)号：US12171090B2

    公开(公告)日：2024-12-17

    申请号：US18209988

    申请日：2023-06-14

    Applicant: Intel Corporation

    Inventor： Zheng Guo ,  Clifford L. Ong ,  Eric A. Karl ,  Mark T. Bohr

    IPC: H10B10/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

    Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

    Metal-free frame design for silicon bridges for semiconductor packages
    303.
    发明授权
    Metal-free frame design for silicon bridges for semiconductor packages 有权

    公开(公告)号：US12170253B2

    公开(公告)日：2024-12-17

    申请号：US18114123

    申请日：2023-02-24

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

    IPC: H01L23/538 ,  G01R31/27 ,  H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/544 ,  H01L23/58 ,  H01L23/14 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

    Remote traffic performance on cluster-aware processors
    304.
    发明授权
    Remote traffic performance on cluster-aware processors 有权

    公开(公告)号：US12169460B2

    公开(公告)日：2024-12-17

    申请号：US18040944

    申请日：2020-09-18

    Applicant: Intel Corporation

    Inventor： Shijie Liu ,  Tao Xu ,  Lei Zhu ,  Yufu Li

    IPC: G06F13/16 ,  G06F13/10 ,  G06F13/42

    Abstract: Embodiments are directed to improving remote traffic performance on cluster-aware processors. An embodiment of a system includes at least one processor package comprising a plurality of processor ports and a plurality of system agents; and a memory device to store platform initialization firmware to cause the processing system to: determine first locations of the plurality of processor ports in the at least one processor package; determine second locations of the plurality of system agents in the at least one processor package; associate each of the processor ports with a set of the plurality of system agents based on the determined first and second locations; and program the plurality of system agents with the associated processor port for the respective system agent.

    IMPROVING SIZE AND EFFICIENCY OF DIES
    306.
    发明申请
    IMPROVING SIZE AND EFFICIENCY OF DIES 有权

    公开(公告)号：US20240413089A1

    公开(公告)日：2024-12-12

    申请号：US18806287

    申请日：2024-08-15

    Applicant: Intel Corporation

    Inventor： Mathew J. MANUSHAROW ,  Jonathan ROSENFELD

    IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065

    Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

    Hybrid PHY with interleaved and non-interleaved RS-FEC and FEC mode determination during adaptive link training protocol
    309.
    发明授权
    Hybrid PHY with interleaved and non-interleaved RS-FEC and FEC mode determination during adaptive link training protocol 有权

    公开(公告)号：US12166579B2

    公开(公告)日：2024-12-10

    申请号：US18199697

    申请日：2023-05-19

    Applicant: Intel Corporation

    Inventor： Kent Lusted

    IPC: H04L1/00 ,  H03M13/15 ,  H03M13/17

    Abstract: Apparatus and methods for implementing high-speed Ethernet links using a hybrid PHY (Physical layer) selectively configurable to employ a non-interleaved RS-FEC (Reed Solomon Forward Error Correction) sublayer or an interleaved RS-FEC sublayer. An adaptive link training protocol is used during link training to determine whether to employ the non-interleaved or interleaved RS-FEC during link DATA mode. Training frames are exchanged between link partners including control and status fields used to respectfully request a non-interleaved or interleaved FEC mode and confirm the requested FEC mode is to be used during link DATA mode. The hybrid PHY includes interleaved RS-FEC and non-interleaved RS-FEC sublayers for transmitter and receiver operations. During link training, a determination is made to whether a local receiver is likely to see decision feedback equalizer (DFE) burst errors. If so, the interleaved FEC mode is selected; otherwise the non-interleaved FEC mode is selected or is the default FEC mode. The apparatus and methods may be implemented for 100 GB ASE-CR1 and 100 GB ASE-KR1 Ethernet links and interfaces.

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