公开(公告)号：US09306550B2

公开(公告)日：2016-04-05

申请号：US14216719

申请日：2014-03-17

Applicant: STMicroelectronics International N.V.

Inventor： Ravinder Kumar

IPC: H03K3/3565

CPC classification number: H03K3/3565

Abstract: A Schmitt Trigger is implemented in FDSOI technology. The Schmitt Trigger includes a first inverting stage having an NMOS and PMOS transistor having their drains tied together. The NMOS and PMOS transistor each have a first gate coupled to the input voltage and a back gate coupled to the output of the Schmitt Trigger.

Abstract translation: 施密特触发器采用FDSOI技术实现。 施密特触发器包括具有连接在一起的NMOS和PMOS晶体管的第一反相级。 NMOS和PMOS晶体管各自具有耦合到输入电压的第一栅极和耦合到施密特触发器的输出的后栅极。

公开(公告)号：US09294106B2

公开(公告)日：2016-03-22

申请号：US14323794

申请日：2014-07-03

Applicant: STMicroelectronics International N.V.

Inventor： Abhirup Lahiri ,  Nitin Gupta

IPC: H03L7/06 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/093 ,  H03L7/089

Abstract: According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.

Abstract translation: 根据实施例，电路包括被配置为在第一节点处产生第一电流的第一电荷泵，被配置为在第二节点处产生第二电流的第二电荷泵，耦合在第一和第二节点之间的环路滤波器， 环路滤波器，包括耦合到第一节点的第一滤波器路径，耦合到第二节点的第二滤波器路径以及插在第一和第二滤波器路径之间的隔离缓冲器。 第二节点处的第二个电流与第一节点处的第一个电流不同。 该电路还包括一个振荡器，被配置为对第一滤波器路径的输出施加第一增益，并将第二增益应用于第二滤波器路径的输出。

公开(公告)号：US09268894B2

公开(公告)日：2016-02-23

申请号：US14279587

申请日：2014-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma ,  Manoj Sharma Kumar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077

Abstract: A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.

Abstract translation: 用于设计驱动器布局的计算机化方法包括分析原理图电路。 耦合在第一公共节点之间的PMOSFET被分组成一个或多个第一类。 耦合在第二公共节点之间的NMOSFET被分组成一个或多个第二类。 该方法还包括通过生成包括主MOSFET PCELL和主保护环PCELL的超参数化单元（PCELL）布局块来为驱动器的布局区域中的每个位置处的每个MOSFET生成布局，用于第一类和 二等。 主MOSFET PCELL包括MOSFET的第一组参数，主保护环PCELL包括围绕MOSFET的保护环的第二组参数。 主MOSFET PCELL和主保护环PCELL的子PCELL在布局区域的每个位置实例化。

公开(公告)号：US09264049B2

公开(公告)日：2016-02-16

申请号：US14086110

申请日：2013-11-21

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil Bahl ,  Shray Khullar

IPC: G01R31/28 ,  H03L7/06

CPC classification number: H03L7/06 ,  G01R31/318552 ,  G01R31/318555 ,  G06F1/12

Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.

Abstract translation: 半导体芯片包括能够同步器件上的多个时钟信号的片上时钟控制器（OCC）。 每个OCC控制器接收从一个或多个时钟发生器产生的扫描使能信号和唯一的时钟信号。 接收最慢生成时钟信号的OCC通过内部元稳定寄存器传递，并向处理较快时钟信号的OCC提供外部同步信号。 这些更快时钟的OCC可以使用外部同步信号来同步其时钟并产生测试时钟脉冲。

公开(公告)号：US09225238B2

公开(公告)日：2015-12-29

申请号：US14461780

申请日：2014-08-18

Applicant: STMicroelectronics International N.V.

Inventor： Laurent Chevalier

IPC: H02M3/07 ,  G05F3/02 ,  G06F3/16 ,  H02M1/00

CPC classification number: H02M3/07 ,  G05F3/02 ,  G06F3/165 ,  H02M2001/009 ,  H02M2003/071 ,  H02M2003/072

Abstract: A multi level charge pump circuit may be associated with at least two power supplies, and may provide at least four levels of positive and negative voltage. The multi level charge pump may include first and second fly capacitors, and first and second tank capacitors. A plurality of PMOS transistors and NMOS transistors may allow generation of two high voltage levels and two low voltage levels for the multi level charge pump, the low voltage levels being derived from a charging of the two fly capacitors in series. This multi level charge pump may be embodied in an audio device within a platform without a dedicated SMPS circuit.

Abstract translation: 多级电荷泵电路可以与至少两个电源相关联，并且可以提供至少四个正电压和负电压电平。 多级电荷泵可以包括第一和第二飞电电容器，以及第一和第二容性电容器。 多个PMOS晶体管和NMOS晶体管可以允许为多电平电荷泵产生两个高电压电平和两个低电压电平，低电压电平是从两个串联的两个电容器的充电得到的。 该多电平电荷泵可以体现在平台内的音频装置中，而不需要专用的SMPS电路。

公开(公告)号：US09222974B2

公开(公告)日：2015-12-29

申请号：US14152879

申请日：2014-01-10

Applicant: STMicroelectronics International N.V.

Inventor： V Srinivasan ,  Satinder Singh Malhi ,  Tripti Gupta

IPC: G01R31/3187 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/40

CPC classification number: G01R31/31727 ,  G01R31/318552 ,  G01R31/318594 ,  G01R31/3187

Abstract: A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time.

Abstract translation: 一种使用方法测试集成电路的系统和方法，以减少ATPG和LBIST测试期间的电压降。 在一个实施例中，可以将延迟元件添加到用于产生触发各种电子部件的切换的各种时钟信号的时钟电路。 在另一个实施例中，逻辑电路可以被添加到时钟发生电路以隔离时钟域，以便以特定模式启用每个时钟域中的时钟信号。 在又一个实施例中，用于LBIST测试的捕获阶段可以在每个捕获阶段内是不同步的，使得一个LBIST分区的数据捕获可以与其他LBIST分区的其他捕获阶段的时间不同。 最后，另外的实施例ATPG电路也可以被分割，使得逻辑电路一次只能启用一个（或少于所有）ATPG分区。

公开(公告)号：US20150371588A1

公开(公告)日：2015-12-24

申请号：US14725112

申请日：2015-05-29

Applicant: STMicroelectronics International N.V.

Inventor： Jerome Nebon ,  Christophe Forel

IPC: G09G3/32 ,  G09G3/20

CPC classification number: G09G3/3258 ,  G09G3/2003 ,  G09G3/2081 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0866 ,  G09G2320/0233 ,  G09G2320/0242 ,  G09G2320/0626 ,  G09G2330/028

Abstract: A device includes a matrix of active pixels. Each active pixel includes an OLED and a control circuit configured to refresh the active pixel and including at least one transistor having a first conduction terminal coupled to a supply line and a second conduction terminal coupled to the OLED. Supply circuitry is configured to apply a supply voltage to the supply line of each active pixel during the refreshing of the active pixel and for a time period less than a duration of the refreshing of the active pixel.

Abstract translation: 设备包括有源像素的矩阵。 每个有源像素包括OLED和被配置为刷新有源像素并且包括至少一个具有耦合到电源线的第一导电端子和耦合到OLED的第二导电端子的晶体管的控制电路。 电源电路被配置为在刷新有源像素期间以及在刷新有源像素的持续时间的时间周期内向每个有源像素的电源线施加电源电压。

公开(公告)号：US20150366026A1

公开(公告)日：2015-12-17

申请号：US14723942

申请日：2015-05-28

Applicant: STMicrolelectronics International N.V.

Inventor： Jerome Nebon ,  Christophe Forel

IPC: H05B33/08 ,  H01L27/32

CPC classification number: H05B33/0896 ,  G09G3/3233 ,  G09G2300/0814 ,  G09G2320/0247 ,  G09G2320/045

Abstract: An integrated device includes a semiconducting substrate having a matrix of active pixels formed therein. Each active pixel includes an OLED diode, a first nMOS transistor having its source coupled to an anode of the OLED diode, and a refresh circuit coupled to a gate of the first nMOS transistor. The first nMOS transistor has its source and its substrate coupled together. The first nMOS transistor is situated in and on a first part of the semiconductor substrate, and the refresh circuit is situated in and on a second part of the semiconductor substrate, with the first part and the second part being electrically insulated from one another.

Abstract translation: 集成器件包括其中形成有有源像素的矩阵的半导体衬底。 每个有源像素包括OLED二极管，其源极耦合到OLED二极管的阳极的第一nMOS晶体管，以及耦合到第一nMOS晶体管的栅极的刷新电路。 第一个nMOS晶体管具有其源极及其衬底耦合在一起。 第一nMOS晶体管位于半导体衬底的第一部分中并且位于半导体衬底的第一部分上，并且刷新电路位于半导体衬底的第二部分中并位于半导体衬底的第二部分上，其中第一部分和第二部分彼此电绝缘。

公开(公告)号：US20150330778A1

公开(公告)日：2015-11-19

申请号：US14281273

申请日：2014-05-19

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas Kumar Sinha ,  Nishant Omar

IPC: G01B21/00

CPC classification number: G01B21/00 ,  G01C21/16 ,  G06K9/00348 ,  H05B37/029

Abstract: Methods and systems for dynamic tracking of on-stage objects using microelectromechanical systems (MEMS) presented herein do not require illumination to track a randomly moving object and are easily configurable for various stage sizes and for stages movable relative to the ground. In some instances, a tracking method includes determining an initial state of an MEMS motion tracker carried on a dynamic object, such as a performer. Acceleration and orientation information gathered by the motion tracker is monitored. A change of state in response to the monitored acceleration and orientation information is then determined. An instant state is calculated using the change of state and the initial state. Actuation signals based on the calculated instant state are generated for actuating a gimbal. The gimbal faces a device supported thereby toward the dynamic object.

Abstract translation: 使用本文中提出的微机电系统（MEMS）对现场物体的动态跟踪的方法和系统不需要照明来跟踪随机移动的物体，并且可以容易地配置用于各种舞台尺寸和相对于地面可移动的舞台。 在一些情况下，跟踪方法包括确定在诸如执行者之类的动态对象上承载的MEMS运动跟踪器的初始状态。 监测运动跟踪器收集的加速度和姿态信息。 然后确定响应于监视的加速度和方位信息的状态改变。 使用状态的改变和初始状态计算即时状态。 产生基于计算出的瞬时状态的致动信号用于致动万向节。 万向架面向由此支撑的设备朝向动态对象。

公开(公告)号：US09191025B1

公开(公告)日：2015-11-17

申请号：US14502360

申请日：2014-09-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anubhuti Chopra

IPC: H03M1/66 ,  H03M1/68 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46 ,  H03M3/00

CPC classification number: H03M1/687 ,  H03M1/0626 ,  H03M1/0665 ,  H03M1/1245 ,  H03M1/462 ,  H03M3/464

Abstract: In an embodiment, a digital-to-analog converter (DAC) converts an input digital signal into an output analog signal, and includes first and second segments, a combiner, and a controller. The first segment includes a first number of first elements that are configured to generate a first analog signal in response to a first portion of the digital signal, and the second segment includes a second number of second elements that are configured to generate a second analog signal in response to a second portion of the digital signal. The combiner is configured to combine the first analog signal and the second analog signal to generate the output analog signal, and the controller is configured to deactivate one of the first elements and to activate one of the second elements in place of the deactivated first element. For example, such a segmented DAC may be suitable for use in a sigma-delta ADC.

Abstract translation: 在一个实施例中，数模转换器（DAC）将输入数字信号转换为输出模拟信号，并且包括第一和第二段，组合器和控制器。 第一段包括第一数量的第一元件，其被配置为响应于数字信号的第一部分产生第一模拟信号，并且第二段包括第二数量的第二元件，其被配置为产生第二模拟信号 响应于数字信号的第二部分。 组合器被配置为组合第一模拟信号和第二模拟信号以产生输出模拟信号，并且控制器被配置为去激活第一元件中的一个并且激活第二元件中的一个代替去激活的第一元件。 例如，这种分段DAC可适用于Σ-ΔADC。