公开(公告)号：US12143015B2

公开(公告)日：2024-11-12

申请号：US17731000

申请日：2022-04-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sebastien Ortet

IPC: H02M3/158

Abstract: In an embodiment a switching power supply includes a voltage ramp generator comprising at least one output capacitor, wherein the generator is configured such that the output capacitor has a first value during a first operating cycle of a first operating mode and a second value during subsequent operating cycles of the first operating mode.

公开(公告)号：US12140483B2

公开(公告)日：2024-11-12

申请号：US17452224

申请日：2021-10-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  Bruno Gailhard

IPC: G01K15/00 ,  G01K7/00 ,  G01K7/20 ,  G01K7/01

Abstract: A calibration method of a temperature sensor is provided. The temperature sensor having a current source and a ring oscillator generating a square pulse signal with a temperature-dependent square pulse frequency. The acquisition of a first square pulse frequency measurement at a first temperature from the square pulse signal forms a first measurement point. A second square pulse frequency measurement at a second temperature from the second square pulse signal forms a second measurement point. The determination of the relation data being representative of an affine relation between square pulse frequency measurements and temperatures. The affine relation being defined by a used proportionality coefficient modified with respect to a measured proportionality coefficient of a measured affine relation linking the first measurement point and the second measurement point.

公开(公告)号：US12107504B2

公开(公告)日：2024-10-01

申请号：US17571759

申请日：2022-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sebastien Ortet ,  Vincent Binet

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/1588 ,  H02M1/0009

Abstract: In an embodiment, a switching power supply includes: an output stage; a clock generator configured to generate a first clock signal; and a control circuit configured to control the output stage based on the first clock signal, wherein the switching power supply is configured to have a first operating mode synchronized by the first clock signal, and a second operating mode that is asynchronous, wherein the clock generator is configured to maintain the first clock signal at a constant value during the second operating mode.

公开(公告)号：US20240324196A1

公开(公告)日：2024-09-26

申请号：US18735967

申请日：2024-06-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Melul ,  Abderrezak Marzaki ,  Madjid Akbal

IPC: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10

CPC classification number: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L29/66825 ,  H01L29/7884 ,  H01L29/40114 ,  H01L29/7883 ,  H10B41/10

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.

公开(公告)号：US12072755B2

公开(公告)日：2024-08-27

申请号：US17951631

申请日：2022-09-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Denis Roman ,  Jean-Louis Demessine ,  Lionel Chastillon ,  Renaud Lemonnier

IPC: G06F1/32 ,  G06F1/3296 ,  H04B5/77

CPC classification number: G06F1/3296 ,  H04B5/77

Abstract: The present description concerns an electronic device having an antenna configured to receive a radio frequency signal. The electronic device further includes a control unit. The control unit is off, and the antenna receives a radio frequency signal. The antenna is configured to deliver a first voltage representative of the radio frequency signal to power the control unit with the voltage for the duration of the booting of the control unit.

公开(公告)号：US12058255B2

公开(公告)日：2024-08-06

申请号：US17553481

申请日：2021-12-16

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Julien Couvrand ,  William Orlando

IPC: H04L9/08

CPC classification number: H04L9/0894

Abstract: The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.

公开(公告)号：US12057513B2

公开(公告)日：2024-08-06

申请号：US18210155

申请日：2023-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Brice Arrazat ,  Julien Delalleau ,  Joel Metz

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/94 ,  H01L49/02 ,  H10B41/35

CPC classification number: H01L29/945 ,  H01L21/2652 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/788 ,  H10B41/35

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US20240232342A9

公开(公告)日：2024-07-11

申请号：US18487697

申请日：2023-10-16

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Thomas SARNO

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: A device includes a memory and cryptographic processing circuitry coupled to the memory. The memory, in operation, stores one or more lookup tables. The cryptographic processing circuitry, in operation, processes masked data and protects the processing of masked data against side channel attacks. The protecting includes applying masked binary logic operations to masked data using lookup tables of the one or more lookup tables.

公开(公告)号：US20240201773A1

公开(公告)日：2024-06-20

申请号：US18081011

申请日：2022-12-14

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sylvain CHAVAGNAT ,  Simon VALCIN

IPC: G06F1/3234

CPC classification number: G06F1/3243

Abstract: Disclosed herein is a debug system including a host computer, a microcontroller, and a debug probe for interface therebetween for performing debug trace operations. The debug probe samples the current drawn by the microcontroller. The debug probe and host computer cooperate so as to acquire and accurately align trace data and the samples of the current drawn by the microcontroller. Techniques for performing this alignment are described herein and enable for accurate inferences to be drawn about the current drawn by the microcontroller during different program operations.

公开(公告)号：US20240136350A1

公开(公告)日：2024-04-25

申请号：US18485190

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Loic BOURGUINE ,  Lionel ESTEVE

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L27/0285 ,  H01L27/0288 ,  H01L28/24 ,  H01L29/2003 ,  H01L29/7787

Abstract: The present disclosure concerns overtemperature protection circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising:



a first resistor having a first positive temperature coefficient and being arranged in said gallium nitride layer; and
a second resistor having a second temperature coefficient different from the first coefficient.