公开(公告)号：US10832967B2

公开(公告)日：2020-11-10

申请号：US16101963

申请日：2018-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Garo Jacques Derderian

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.

公开(公告)号：US10825897B2

公开(公告)日：2020-11-03

申请号：US16262052

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/78 ,  H01L21/28

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.

公开(公告)号：US10818659B2

公开(公告)日：2020-10-27

申请号：US16161294

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Hui Zang ,  Guowei Xu ,  Scott Beasor

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.

公开(公告)号：US10811422B2

公开(公告)日：2020-10-20

申请号：US16196060

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Wei Hong ,  Hui Zang ,  David P. Brunco

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/08

Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.

公开(公告)号：US10804379B2

公开(公告)日：2020-10-13

申请号：US15980436

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Scott Beasor

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/28

Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an α-Si layer in a recess over the epi S/D; forming an oxide layer over the α-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and α-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.

公开(公告)号：US10741656B2

公开(公告)日：2020-08-11

申请号：US16121014

申请日：2018-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3213

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.

公开(公告)号：US10727067B2

公开(公告)日：2020-07-28

申请号：US16203816

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  David P. Brunco

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49

Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.

公开(公告)号：US10714577B2

公开(公告)日：2020-07-14

申请号：US16149711

申请日：2018-10-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hui Zang ,  Hsien-Ching Lo

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/165 ,  H01L29/78 ,  H01L21/84 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. First and second device structure are respectively formed in first and second device regions, and a first dielectric layer is formed over the first and second device regions. The first dielectric layer includes a recess defining a step at a transition between the first and second device regions, and a second dielectric layer is arranged within the recess in the first dielectric layer. A third dielectric layer is arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region. A contact, which is coupled with the second device structure, extends through the first, second, and third dielectric layers in the second device region.

公开(公告)号：US10707207B1

公开(公告)日：2020-07-07

申请号：US16277496

申请日：2019-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Dali Shao

IPC: H01L21/20 ,  H01L29/94 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device, comprising first and second sets of fins; first and second gate electrodes; first and second isolation structures each separating one of the gate electrodes into a first portion and a second portion; and first and second conductive structures wider than the corresponding isolation structure and disposed on an entirety of a top of the corresponding isolation structure and on a part of the top of each of the first and second portions of the corresponding gate electrode. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device. The semiconductor device may have a low parasitic capacitance and high chip performance.

公开(公告)号：US10692812B2

公开(公告)日：2020-06-23

申请号：US15980085

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ravi Prakash Srivastava ,  Hui Zang ,  Jiehui Shu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/308 ,  H01L21/02 ,  H01L21/033

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.