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    ENHANCING NUCLEATION IN PHASE-CHANGE MEMORY CELLS
    311.
    发明申请
    ENHANCING NUCLEATION IN PHASE-CHANGE MEMORY CELLS 有权
    在相变记忆细胞中增强核酸

    公开(公告)号：US20160254050A1

    公开(公告)日：2016-09-01

    申请号：US15154410

    申请日：2016-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Davide Fugazza ,  Johannes A. Kalb

    IPC: G11C13/00

    CPC classification number: G11C13/0004 ,  G11C7/04 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092

    Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

    Abstract translation: 本文公开的各种实施例包括用于将存储器阵列的相变存储器（PCM）单元放置在其中在应用随后的SET编程信号之前增强PCM单元的成核概率的温度状态的方法和装置。 在一个实施例中，该方法包括将成核信号施加到PCM单元以在存储器阵列内形成成核位置，其中成核信号具有非零上升沿。 随后施加编程信号以在所述多个PCM单元的选定的单元内实现期望的结晶度。 还描述了附加的方法和装置。

    APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE
    313.
    发明申请
    APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE 有权
    基于对测试脉冲的响应来读取记忆细胞的装置和方法

    公开(公告)号：US20160163383A1

    公开(公告)日：2016-06-09

    申请号：US14977411

    申请日：2015-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0057

    Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

    Abstract translation: 所公开的技术通常涉及其操作的存储装置和方法，更具体地涉及读取存储器阵列（诸如交叉点存储器阵列）中的存储器单元的存储器阵列和方法。 在一个方面，所述方法包括提供包括以多种状态之一的存储器单元的存储器阵列。 该方法还包括确定存储器单元的阈值电压（Vth）是否具有在预定读取电压窗口内的值。 如果确定阈值电压具有预定读取电压窗口内的值，则将测试脉冲施加到存储器单元。 可以基于存储器单元对测试脉冲的响应来确定存储器单元的状态，其中该状态在接收测试脉冲之前对应于存储单元的多个状态中的一个状态。

    Memory arrays and methods of forming same
    314.
    发明授权
    Memory arrays and methods of forming same 有权
    存储阵列及其形成方法

    公开(公告)号：US09343670B2

    公开(公告)日：2016-05-17

    申请号：US14268587

    申请日：2014-05-02

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Antonino Rigano

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/122 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

    Abstract: Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.

    Abstract translation: 提供了存储器阵列及其形成方法。 形成存储器阵列的一个示例性方法可以包括使用自对准多图案化技术形成具有环形特征的第一导电材料，以及在环形特征上形成第一密封材料。 在第一密封材料上方形成第一剁掩模材料。 环状特征和第一密封材料在第一剁掩模材料外移除。

    Memory Arrays and Methods of Forming Memory Cells
    319.
    发明申请
    Memory Arrays and Methods of Forming Memory Cells 有权

    公开(公告)号：US20130341587A1

    公开(公告)日：2013-12-26

    申请号：US13974641

    申请日：2013-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    IPC: H01L45/00

    CPC classification number: H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

    Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

    MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE
    320.
    发明申请
    MEMORY DEVICE WITH A SPLIT PILLAR ARCHITECTURE 有权

    公开(公告)号：US20250159910A1

    公开(公告)日：2025-05-15

    申请号：US18952568

    申请日：2024-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Paolo Fantini

    IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.

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