公开(公告)号：US20080205346A1

公开(公告)日：2008-08-28

申请号：US11712595

申请日：2007-02-27

Applicant: Andrea Concil ,  Andrea Giorgi ,  Rizziero Gorla

Inventor： Andrea Concil ,  Andrea Giorgi ,  Rizziero Gorla

IPC: H04B7/216

CPC classification number: H04L1/0044 ,  H04L1/0068 ,  H04L1/08

Abstract: An embodiment of a telecommunication transmitter/receiver device is provided. The transmitter device includes: means for providing a set of words, each word including a plurality of digital symbols; a first memory area for storing the set of words, the first memory area including a first sequence of memory locations each one for storing a symbol; a second memory area for storing a composite frame including a predetermined number of symbols, the second memory area including a second sequence of memory locations; conversion means for converting the set of words in the first memory area into the frame in the second memory area, the conversion means including reduction means for reducing each word by removing a set of symbols from the word according to a puncturing algorithm, and expansion means for expanding each word by adding a set of additional symbols to the word according to a repeating algorithm; and means for transmitting the frame. The first memory area and the second memory area have at least one memory location in common. The receiver device has a dual structure.

Abstract translation: 提供了一种电信发射机/接收机设备的实施例。 发射机设备包括：用于提供一组单词的装置，每个单词包括多个数字符号; 用于存储所述一组单词的第一存储区域，所述第一存储区域包括每个用于存储符号的存储器位置的第一序列; 第二存储区域，用于存储包括预定数量符号的复合帧，所述第二存储区域包括第二存储器位置序列; 转换装置，用于将第一存储区域中的单词集合转换成第二存储区域中的帧，转换装置包括缩减装置，用于通过根据打孔算法从单词中去除一组符号来减少每个单词;扩展装置 用于通过根据重复算法向该单词添加一组附加符号来扩展每个单词; 以及用于发送帧的装置。 第一存储器区域和第二存储器区域具有至少一个共同的存储器位置。 接收机设备具有双重结构。

公开(公告)号：US20080179697A1

公开(公告)日：2008-07-31

申请号：US12006819

申请日：2008-01-04

Applicant: Mario Cortese ,  Mark Anthony Azzopardi ,  Edward Myers ,  Chantal Combi ,  Lorenzo Baldo

Inventor： Mario Cortese ,  Mark Anthony Azzopardi ,  Edward Myers ,  Chantal Combi ,  Lorenzo Baldo

IPC: H01L29/84 ,  H01L21/58

CPC classification number: B81B7/0061 ,  B81B7/007 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free.

Abstract translation: 电子设备包括设置有通过开口的基板和包括活性表面的MEMS器件，其中MEMS器件的一部分对流体的化学/物理变化敏感。 MEMS器件的有源表面面向衬底并与其间隔开，敏感部分与开口对准。 保护封装至少部分地包括MEMS器件和衬底，至少留下MEMS器件的敏感部分，并暴露衬底的开口。 屏障元件位于围绕敏感部分的区域中，以实现用于MEMS器件的保护结构，使得敏感部分是自由的。

公开(公告)号：US20080158370A1

公开(公告)日：2008-07-03

申请号：US12048756

申请日：2008-03-14

Applicant: Fabio Pasolini ,  Luca Fontanella

Inventor： Fabio Pasolini ,  Luca Fontanella

IPC: H04N5/228

CPC classification number: G01P15/125 ,  G01P15/18 ,  G01P2015/082 ,  G01P2015/0831 ,  H04N5/23248 ,  H04N5/23258 ,  H04N5/23287

Abstract: A device for stabilizing images acquired by a digital-image sensor includes a motion-sensing device, for detecting quantities correlated to pitch and yaw movements of the digital-image sensor, and a processing unit, connectable to the digital-image sensor for receiving a first image signal and configured for extracting a second image signal from the first image signal on the basis of the quantities detected by the motion-sensing device. The motion-sensing device includes a first accelerometer and a second accelerometer.

Abstract translation: 用于稳定由数字图像传感器获取的图像的装置包括用于检测与数字图像传感器的俯仰和偏航运动相关的量的运动感测装置，以及可连接到数字图像传感器的处理单元，用于接收 第一图像信号，并且被配置为基于由运动感测装置检测到的量从第一图像信号中提取第二图像信号。 运动感测装置包括第一加速度计和第二加速度计。

公开(公告)号：US20080089125A1

公开(公告)日：2008-04-17

申请号：US11895609

申请日：2007-08-24

Applicant: Rino Micheloni ,  Giovanni Campardo

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C16/04

CPC classification number: G11C16/08

Abstract: An embodiment of a non-volatile memory device is provided. The memory device includes a memory matrix comprising a plurality of memory cells, arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines; each word line is associated with one respective row of said plurality and is connected to the memory cells of the row; the word lines are grouped into at least one packet. The memory device includes a row selector coupled to the word lines and adapted to selectively biasing them. The row selector includes, for each packet of word lines, a plurality of first paths, wherein each first path is adapted to apply a first biasing voltage to a corresponding word line of the packet depending on an operation to be performed on the memory cells connected to the corresponding word line. Each first path includes at least a first and a second selection transistors series-connected between a first terminal and a second terminal of the first path. The second terminal is coupled to the corresponding word line. The memory device further includes enabling means for commonly providing an enabling voltage to the first terminal of the first paths associated to a selected packet of word lines including a selected word line. The enabling voltage depends on the operation to be performed on the memory cells connected to the selected word line and is adapted to enable the execution of said operation. The memory device further includes selection means for selecting one among said plurality of first paths. the selected first path corresponding to the selected word line. The selection means are adapted to activate the first selection transistor of the selected first path in order to obtain the first biasing voltage from the enabling voltage by a voltage drop introduced by the first selection transistor; said selection means are further adapted to activate the second selection transistor of the selected first path in order to transfer the first biasing voltage provided by the first selection transistor onto the selected word line.

公开(公告)号：US20070183201A1

公开(公告)日：2007-08-09

申请号：US11615349

申请日：2006-12-22

Applicant: Giuseppe Cina ,  Lorenzo Todaro

Inventor： Giuseppe Cina ,  Lorenzo Todaro

IPC: G11C16/04

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.

Abstract translation: 集成在第一类型导电体的半导体衬底上的非易失性存储器件，包括被称为位线的称为字线的行（被称为字线）和列的非易失性存储器单元矩阵，该器件包括多个等距间隔的有源 具有集成在其中的非易失性存储单元的区域，每个非易失性存储单元具有耦合到控制栅电极的源极区，漏区和浮栅，一组存储单元共享共同源极线 第二类型的导电性，在与公共源极线电接触的多个有源区域中的至少一个中的所述第二导电类型的注入区域以及与所述注入区域对准并电接触的至少一个源极触点。

公开(公告)号：US20070176208A1

公开(公告)日：2007-08-02

申请号：US11215348

申请日：2005-08-30

Applicant: Danilo Mascolo ,  Gianfranco Cerofolini ,  Gianguido Rizzotto

Inventor： Danilo Mascolo ,  Gianfranco Cerofolini ,  Gianguido Rizzotto

IPC: H01L27/10

CPC classification number: H01L51/0021 ,  G11C2213/77 ,  H01L27/285 ,  H01L51/0595 ,  Y10S257/90 ,  Y10S977/712 ,  Y10S977/72 ,  Y10S977/722 ,  Y10S977/723

Abstract: A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.

Abstract translation: 描述了纳米级元件的托管结构，其包括衬底，第一多间隔物层，包括第一多个间隔物，其包括彼此平行的第一导电间隔物，以及在所述第一多间隔物层上方实现的至少第二多间隔物水平 并且包括横向于所述第一多个间隔件布置的第二多个间隔件，并且至少包括下部不连续绝缘层和上层，其又包括第二导电间隔件。 特别地，第二多间隔物级别的每对间隔物限定第一多间隔物层的间隔物，多个纳米托管座具有至少第一和第二导电端子，该第一和第二导电端子由第一导电间隔物的部分实现， 的第二导电隔离物面向主机座。 还描述了制造这种结构的方法。

公开(公告)号：US20070166980A1

公开(公告)日：2007-07-19

申请号：US11312232

申请日：2005-12-19

Applicant: Jong-Won Lee ,  Roger Hamamjy

Inventor： Jong-Won Lee ,  Roger Hamamjy

IPC: H01L21/44

CPC classification number: C23C16/34 ,  C23C16/4482 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1683

Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times. Two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.

Abstract translation: 有机金属前体可用于形成用作相变存储器的加热器的氮化钛膜。 通过使用TDMAT和TrDMASi的组合，例如在金属有机化学气相沉积室中，可以在合理的沉积时间内实现相对高百分比的硅。 可以使用两个单独的起泡器将气态的两种有机金属化合物进料到沉积室，以便容易地控制前体的相对比例。

公开(公告)号：US20070109856A1

公开(公告)日：2007-05-17

申请号：US11557786

申请日：2006-11-08

Applicant: Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

Inventor： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

IPC: G11C16/06

CPC classification number: G11C29/76 ,  G11C29/006 ,  G11C2029/1208

Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

Abstract translation: 在包括分组在数据存储单元块中的单元阵列的非易失性存储器件中的管理失败的方法包括在阵列中定义用户可寻址的单元块的第一子集以及单元的冗余块的第二子集。 在非易失性存储器件的晶片上的测试期间，包括第一子集中的至少一个故障单元的每个块被定位。 每个块被标记为坏，并且各个代码的坏块地址表存储在非易失性存储器缓冲器中。 在上电时，坏块地址表从非易失性存储器缓冲区复制到随机存取存储器。 通过查找坏块地址表来验证第一子集的存储器单元的块是坏的，并且如果块是坏的，则重新映射对相应的冗余单元块的访问。 在阵列中定义了非用户可寻址单元块的第三子集，用于存储第三子块的块的可寻址寻址页的各个代码的坏块地址表。 第三子集的每一页与相应的冗余块相关联。 如果在存储器件的工作寿命期间，在测试阶段中先前判断良好的一个单元的块变得失败，则每个块被标记为坏，并且随机存取存储器中存储的表被更新。

公开(公告)号：US20070097767A1

公开(公告)日：2007-05-03

申请号：US11265781

申请日：2005-11-01

Applicant: Alberto Taddeo

Inventor： Alberto Taddeo

IPC: G11C7/02

CPC classification number: G11C7/02 ,  G11C7/062 ,  G11C7/14 ,  G11C16/28

Abstract: A wheeled machine that rakes lawns and other surfaces to remove leaves, pine needles and other lightweight debris and conveys this material directly into a standard size plastic bag for disposal or transport to a composting location.

Abstract translation: 一台轮式机器，用于耙草坪和其他表面，以除去叶子，松针和其他轻质碎屑，并将此材料直接输送到标准尺寸的塑料袋中，以便处理或运输到堆肥场所。

公开(公告)号：US20070053377A1

公开(公告)日：2007-03-08

申请号：US11219358

申请日：2005-09-02

Applicant: Daniele Lo Iacono

Inventor： Daniele Lo Iacono

IPC: H04L12/66

CPC classification number: G06F9/30101 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3885

Abstract: A data processor unit includes at least two operation-execution units, each one adapted to receive input data, perform a respective operation on the input data and outputting output data resulting after applying said operation; the data processor unit further includes: a data storage unit including at least two individually-accessible memory devices adapted to store data; a programmable controller adapted to be programmed so as to execute a selected program; a first data routing circuit arrangement adapted to receive data from the at least two memory devices, from the programmable controller and from a second data routing circuit arrangement, and for selectively routing selected ones among the received data to the input of the operation-execution units; the second data routing circuit arrangement is adapted to receive the output data outputted by the operation-execution units and to selectively route the output data to the at least two memory devices, to the programmable controller, and to the first data routing circuit arrangement. The programmable controller is operatively coupled to the at least two operation-execution units, to the first and second data routing circuit arrangements, and to the at least two memory devices for controlling the operation thereof.

Abstract translation: 数据处理器单元包括至少两个操作执行单元，每个操作执行单元适于接收输入数据，对输入数据执行相应的操作并输出在应用所述操作之后产生的输出数据; 所述数据处理器单元还包括：数据存储单元，包括适于存储数据的至少两个可独立存取的存储器件; 可编程控制器，其被编程为执行所选择的程序; 第一数据路由电路装置，其适于从所述可编程控制器和第二数据路由电路装置接收来自所述至少两个存储器装置的数据，并且用于将所接收的数据中的所选数据选择性地路由到所述操作执行单元的输入 ; 第二数据路由电路装置适于接收由操作执行单元输出的输出数据并选择性地将输出数据路由到至少两个存储器件，可编程控制器和第一数据路由电路装置。 可编程控制器可操作地耦合到至少两个操作执行单元，耦合到第一和第二数据路由电路布置，以及至少两个存储器件，用于控制其操作。