公开(公告)号：US12164322B2

公开(公告)日：2024-12-10

申请号：US17359413

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Mauricio Aguilar Salas ,  Jonathan Douglas ,  Anant Deval

IPC: G05F1/59 ,  G05F1/575 ,  G06F1/3203

Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

公开(公告)号：US12162156B2

公开(公告)日：2024-12-10

申请号：US17133069

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Javier Felip Leon ,  Ignacio Alvarez ,  Maria Soledad Elli ,  David Gonzalez-Aguirre ,  Javier Turek

IPC: B25J9/16 ,  B25J9/00

Abstract: A robotic manipulation planning system, including at least one processor; and a non-transitory computer-readable storage medium including instructions that, when executed by the at least one processor, cause the at least one processor to: process perception data to detect known, familiar, and unknown objects to generate manipulation candidates; filter manipulation candidates against constraints to reduce the manipulation candidates; and determine quality metrics for the reduced manipulation candidates using a soft-body simulation technique.

公开(公告)号：US20240406380A1

公开(公告)日：2024-12-05

申请号：US18798562

申请日：2024-08-08

Applicant: Intel Corporation

Inventor： Qian Xu ,  Jian Hu ,  Navyasree Matturu ,  Dmitry E. Ryzhov ,  Satya N. Yedidi

IPC: H04N19/105 ,  H04N19/176

Abstract: A block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. Some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. It is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. To address this concern, a hardware-efficient process can be implemented to rank and select merge candidates. A reference frame priority list is applied to select a subset of potential reference frame combinations. An efficient top-K sorting algorithm is applied to identify merge candidates for each reference frame combination and keep top merge candidates with highest weights. Motion compensation and rate-distortion optimization are performed on the top merge candidates only.

公开(公告)号：US20240405781A1

公开(公告)日：2024-12-05

申请号：US18326042

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Sophia MAERKOVICH ,  Sarit ZUR ,  Oren Ezra AVRAHAM

IPC: H03M1/46 ,  H03K19/17728 ,  H03M1/40

Abstract: A circuit comprising: an analog-to-digital converter configured to generate a digital signal based on a received input voltage and a received reference voltage; a capacitor array; and a switching network configured to switch each capacitor of the capacitor array between a first conductor connected to a supply voltage source, and a second conductor connected to the reference voltage; wherein the analog-to-digital converter comprises a logic configured to control the switching network to selectively switch between the first conductor and the second conductor based on the generated digital signal.

公开(公告)号：US20240405459A1

公开(公告)日：2024-12-05

申请号：US18327100

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Navneet K. SINGH ,  Aiswarya PIOUS ,  Samarth ALVA ,  Sharvil DESAI ,  Ralph JENSEN ,  Carlos MARISCAL ,  Michael CROCKER ,  Kevin MA ,  Pedro Jose MARTINEZ NARVAEZ

IPC: H01R12/52 ,  H05K3/36

Abstract: According to the various aspects, the present disclosure is directed to printed circuit board assemblies having a plurality of printed circuit board units or modules that use board connectors for joining the printed circuit board units. In an aspect, the board connector has a first surface, which may be a top surface, and an opposing second surface, which may be a bottom surface, and a plurality of openings, including a first set of connector openings for providing electrical connections between the at least two plurality of printed circuit board units. In another aspect, a method that includes forming a first printed circuit board unit with a first connecting portion and a second printed circuit board unit with a second connecting portion, and the first and second connecting are electrically coupled with the printed circuit board connector.

公开(公告)号：US20240405085A1

公开(公告)日：2024-12-05

申请号：US18204204

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Patrick MORROW

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

Abstract: Integrated circuit structures having backside contact stitching are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. First and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. The conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.

公开(公告)号：US20240405006A1

公开(公告)日：2024-12-05

申请号：US18805232

申请日：2024-08-14

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Junnan ZHAO ,  Ying WANG ,  Meizi JIAO

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US20240403620A1

公开(公告)日：2024-12-05

申请号：US18679802

申请日：2024-05-31

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06F7/78 ,  G06F9/00 ,  G06N3/084 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US12160495B2

公开(公告)日：2024-12-03

申请号：US17475200

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Mark Bordogna ,  Jonathan A. Robinson ,  Srinivasan S. Iyengar

IPC: H04L7/00

Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.

公开(公告)号：US12160368B2

公开(公告)日：2024-12-03

申请号：US16859792

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Patrick Connor ,  Patrick G. Kutch ,  John J. Browne ,  Alexander Bachmutsky

IPC: H04L47/78 ,  H04L41/08 ,  H04L41/0816 ,  H04L43/0852 ,  H04L43/0888 ,  H04L47/72

Abstract: Examples described herein relate to a device configured to allocate memory resources for packets received by the network interface based on received configuration settings. In some examples, the device is a network interface. Received configuration settings can include one or more of: latency, memory bandwidth, timing of when the content is expected to be accessed, or encryption parameters. In some examples, memory resources include one or more of: a cache, a volatile memory device, a storage device, or persistent memory. In some examples, based on a configuration settings not being available, the network interface is to perform one or more of: dropping a received packet, store the received packet in a buffer that does not meet the configuration settings, or indicate an error. In some examples, configuration settings are conditional where the settings are applied if one or more conditions is met.