公开(公告)号：US11538813B2

公开(公告)日：2022-12-27

申请号：US16923117

申请日：2020-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285 ,  H01L29/45

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US20220406996A1

公开(公告)日：2022-12-22

申请号：US17377367

申请日：2021-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.

公开(公告)号：US11527710B2

公开(公告)日：2022-12-13

申请号：US16529779

申请日：2019-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Jou Lee ,  Kun-Chen Ho ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

公开(公告)号：US11527428B2

公开(公告)日：2022-12-13

申请号：US16931277

申请日：2020-07-16

Applicant: United Microelectronics Corp.

Inventor： Nuo Wei Luo ,  Huabiao Wu

IPC: H01L21/68 ,  H01L21/027 ,  G03F7/20 ,  H01L23/544

Abstract: Provided is a method of manufacturing a semiconductor device, including providing a substrate including a first region and a second region; forming an alignment mark in the substrate in the second region; forming a material layer on a first surface of the substrate in the first region and the second region; introducing heteroatoms into the substrate in the second region from a second surface of the substrate; and reacting the heteroatoms with the substrate to form a dielectric layer overlapping the alignment mark in the substrate in the second region.

公开(公告)号：US20220393103A1

公开(公告)日：2022-12-08

申请号：US17363023

申请日：2021-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.

公开(公告)号：US20220392850A1

公开(公告)日：2022-12-08

申请号：US17369936

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chin-Chia Yang ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/00 ,  H01L23/522 ,  H01L29/417 ,  H01L21/02

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

公开(公告)号：US20220392768A1

公开(公告)日：2022-12-08

申请号：US17341183

申请日：2021-06-07

Applicant: United Microelectronics Corp.

Inventor： Yi Jing Wang ,  Chia-Chang Hsu ,  Chien-Hao Chen ,  Chang-Mao Wang ,  Chun-Chi Yu

IPC: H01L21/033 ,  H01L21/311 ,  H01L23/544 ,  H01L21/66 ,  G03F7/20

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

公开(公告)号：US20220384254A1

公开(公告)日：2022-12-01

申请号：US17883647

申请日：2022-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-How Chou ,  Tzu-Hao Fu ,  Tsung-Yin Hsieh ,  Chih-Sheng Chang ,  Shih-Chun Tsai ,  Kun-Chen Ho ,  Yang-Chou Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

公开(公告)号：US20220384139A1

公开(公告)日：2022-12-01

申请号：US17369077

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zheng-Yang LI ,  Chian-Chen KUO ,  Yi-Cheng LU ,  Ji-Fu KUNG

IPC: H01J37/08 ,  H01L21/67 ,  H01J37/305 ,  H01J27/18

Abstract: An automatic adjustment method and an automatic adjustment device of a beam of a semiconductor apparatus, and a training method of a parameter adjustment model are provided. The automatic adjustment method of the beam of the semiconductor apparatus includes the following steps. The semiconductor apparatus generates the beam. A wave curve of the beam is obtained. The wave curve is segmented into several sections. The slope of each of the sections is obtained. Several environmental factors of the semiconductor apparatus are obtained. According to the slopes and the environmental factors, at least one parameter adjustment command of the semiconductor apparatus is analyzed through the parameter adjustment model.

公开(公告)号：US11515404B2

公开(公告)日：2022-11-29

申请号：US17160427

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Ta-Wei Chiu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/11 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/092 ,  H01L27/02

Abstract: A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.