公开(公告)号：US20080283814A1

公开(公告)日：2008-11-20

申请号：US11748440

申请日：2007-05-14

Applicant: Frederick T Chen ,  Ming-Jinn Tsai

Inventor： Frederick T Chen ,  Ming-Jinn Tsai

IPC: H01L47/00 ,  G11C11/00

CPC classification number: H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675

Abstract: A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material.

Abstract translation: 公开了一种用于减少热损失的相变存储元件。 相变存储元件包括复合层，其中复合层包括电介质材料和低热导率材料。 在复合层内形成通孔。 相变材料占据通孔的至少一部分。 复合层包括交替的层或介电材料和低热导率材料的混合物。

公开(公告)号：US07435643B2

公开(公告)日：2008-10-14

申请号：US11463896

申请日：2006-08-11

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/8242

CPC classification number: H01L27/10841 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 所述电容器包括位于所述支柱侧壁下部的第一板，在所述第一板的周边处的作为上部电极的第二板，在所述第二板的外围的第三板与所述第一板电连接以形成 下电极和将第二板与第一和第三板分离的电介质层。 还描述了基于DRAM单元的DRAM阵列和用于制造DRAM阵列的方法。

公开(公告)号：US20080241741A1

公开(公告)日：2008-10-02

申请号：US11745980

申请日：2007-05-08

Applicant: Chen-Ming Huang

Inventor： Chen-Ming Huang

IPC: G11B7/24

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括衬底。 介电层形成在衬底上，并且相变材料层嵌入电介质层中。 第一导电电极也嵌入电介质层中以穿透相变材料层并且垂直于电介质层的顶表面延伸。

公开(公告)号：US20080232670A1

公开(公告)日：2008-09-25

申请号：US11747140

申请日：2007-05-10

Applicant: Jie Hau Li ,  Ping Shan Chen

Inventor： Jie Hau Li ,  Ping Shan Chen

IPC: G06K9/00

CPC classification number: G05B19/4184 ,  G05B2219/32222 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/22

Abstract: A method for finding a defective machine comprises the steps of selecting a searching period in which a plurality of wafer lots including good wafer lots and bad wafer lots passes through machines, acquiring a lot-passing information related to the passing sequence of the wafer lots through the machines, calculating a bad-lot continuity by taking the lot-passing information into account, and determining a defective machine by taking the bad-lot continuity into account. The bad-lot continuity is calculated by the steps of determining an impact period based on the aggregation degree of the bad wafer lots, calculating a bad-lot distribution probability in the impact period, and calculating the bad-lot continuity by taking the bad-lot distribution probability into account.

Abstract translation: 一种用于发现有缺陷的机器的方法包括以下步骤：选择搜索周期，其中包括好的晶片批次和不良晶片批次的多个晶片批次通过机器，获取与晶片批次的通过顺序有关的批次信息通过 机器，通过考虑批次传递信息来计算不良批次的连续性，并通过考虑不良批次的连续性来确定有缺陷的机器。 通过以下步骤计算不良批次连续性：基于不良晶片批次的聚集程度确定影响周期，计算冲击期间的不良批次分配概率，以及通过采用不良批次连续性计算坏批次连续性， 批次分配概率考虑在内。

公开(公告)号：US20080197335A1

公开(公告)日：2008-08-21

申请号：US11976837

申请日：2007-10-29

Applicant: Tu-Hao YU

Inventor： Tu-Hao YU

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer of the pillar structure. A top electrode electrically connects the second electrode layer of the pillar structure.

Abstract translation: 公开了一种存储器件。 柱结构包括第一电极层，覆盖第一电极层的电介质层和覆盖在电介质层上的第二电极层。 相变层覆盖柱结构的周围。 底部电极电连接柱状结构的第一电极层。 顶电极电连接柱结构的第二电极层。

公开(公告)号：US07407886B2

公开(公告)日：2008-08-05

申请号：US11442259

申请日：2006-05-30

Applicant: Hsueh Yi Che

Inventor： Hsueh Yi Che

IPC: H01L21/44

CPC classification number: H01L27/10888

Abstract: A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with respect to the contact plug structure via a doped region isolated by a shallow trench isolation structure. Preferably, the body portion and the two leg portions can be made of the same conductive material selected from the group consisting of polysilicon, doped polysilicon, tungsten, copper and aluminum, while the dielectric block can be made of material selected from the group consisting of borophosphosilicate glass. Particularly, the contact plug can be prepared by dual-damascene technique. Since the overlapped area between the contact plug structure and a word line can be dramatically decreased, the bit line coupling (BLC) can be effectively reduced.

Abstract translation: 用于棋盘动态随机存取存储器的接触插头结构包括主体部分，连接到主体部分的两个腿部部分和位于两个腿部之间的介质块。 每个支脚部分经由由浅沟槽隔离结构隔离的掺杂区域相对于接触插塞结构电连接到以S形方式设置的深沟槽电容器。 优选地，主体部分和两个腿部分可以由选自多晶硅，掺杂多晶硅，钨，铜和铝的相同的导电材料制成，而介电块可以由选自以下的材料制成： 硼磷硅酸盐玻璃。 特别地，接触插塞可以通过双镶嵌技术制备。 由于可以显着地减小接触插塞结构和字线之间的重叠区域，所以可以有效地减少位线耦合（BLC）。

公开(公告)号：US07402364B2

公开(公告)日：2008-07-22

申请号：US10957678

申请日：2004-10-05

Applicant: Brian S. Lee ,  Chih-Yu Lee

Inventor： Brian S. Lee ,  Chih-Yu Lee

IPC: G03F1/00

CPC classification number: H01L21/32139 ,  G03F1/30 ,  H01L27/10861 ,  H01L27/10891

Abstract: An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.

Abstract translation: 具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。 掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。 通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

公开(公告)号：US20080164504A1

公开(公告)日：2008-07-10

申请号：US11857396

申请日：2007-09-18

Applicant: Wei-Su Chen ,  Yi-Chan Chen ,  Hong-Hui Hsu ,  Chien-Min Lee ,  Der-Sheng Chao ,  Chih-Wei Chen ,  Ming-Jinn Tsai

Inventor： Wei-Su Chen ,  Yi-Chan Chen ,  Hong-Hui Hsu ,  Chien-Min Lee ,  Der-Sheng Chao ,  Chih-Wei Chen ,  Ming-Jinn Tsai

IPC: H01L47/00 ,  H01L21/76

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

Abstract: A phase change memory device is provided. The phase change memory device comprises a substrate. An electrode layer is on the substrate. A phase change memory structure is on the electrode layer and electrically connected to the electrode layer, wherein the phase change memory structure comprises a cup-shaped heating electrode on the electrode layer. An insulating layer is on the cup-shaped heating electrode along a first direction covering a portion of the cup-shaped heating electrode. An electrode structure is on the cup-shaped heating electrode along a second direction covering a portion of the insulating layer and the cup-shaped heating electrode. A pair of double spacers is on a pair of sidewalls of the electrode structure covering a portion of the cup-shaped heating electrode, wherein the double spacer comprises a phase change material spacer and an insulating material spacer on a sidewall of the phase change material spacer.

Abstract translation: 提供了相变存储器件。 相变存储器件包括衬底。 电极层位于基板上。 相变存储器结构在电极层上并电连接到电极层，其中相变存储器结构包括在电极层上的杯形加热电极。 绝缘层沿着覆盖杯状加热电极的一部分的第一方向位于杯状加热电极上。 电极结构沿着覆盖绝缘层和杯状加热电极的一部分的第二方向位于杯状加热电极上。 一对双间隔物位于电极结构的一对侧壁上，覆盖杯状加热电极的一部分，其中双间隔物包括相变材料间隔物和在相变材料间隔物的侧壁上的绝缘材料间隔物 。

公开(公告)号：US07387942B2

公开(公告)日：2008-06-17

申请号：US10732616

申请日：2003-12-09

Applicant: Daniel Wang ,  Chunchieh Huang ,  Dong Jun Kim

Inventor： Daniel Wang ,  Chunchieh Huang ,  Dong Jun Kim

IPC: H01L21/425 ,  H01L21/762

CPC classification number: H01L27/11526 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

公开(公告)号：US20080135943A1

公开(公告)日：2008-06-12

申请号：US11670429

申请日：2007-02-02

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66621 ,  H01L21/28061 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66583

Abstract: A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.

Abstract translation: 提供一种用于制造栅极结构的方法。 衬底氧化物层，焊盘导电层和电介质层依次形成在衬底上。 去除介电层的一部分以形成露出焊盘导电层的一部分的开口。 形成衬垫导电层以覆盖电介质层和焊盘导电层。 去除衬垫导电层的一部分和焊盘导电层的一部分以暴露衬垫氧化物层的表面以形成导电间隔物。 去除衬垫氧化物层，并在衬底上形成栅氧化层。 在栅极氧化物层上顺序地形成第一栅极导电层和第二栅极导电层。 去除栅极氧化物层的一部分，并且覆盖层以填充开口。