公开(公告)号：US20060290358A1

公开(公告)日：2006-12-28

申请号：US11349305

申请日：2006-02-07

Applicant: Carla Motta ,  Giovanni Girlando ,  Alessandro Castorina ,  Giuseppe Palmisano

Inventor： Carla Motta ,  Giovanni Girlando ,  Alessandro Castorina ,  Giuseppe Palmisano

IPC: G01R27/04

CPC classification number: G01R23/20

Abstract: An arrangement is for measuring characteristic parameters of intermodulation distortion of a device under test. The arrangement may include a generator of at least two tones at different test frequencies, and an attenuation path feeding the device with a replica of the two tones attenuated of a factor equal to the gain of the device. The arrangement may also include a circuit for generating a difference signal between the signal output by the device and the two tones, and a circuit input with the difference signal and measuring the characteristic parameters as a function thereof.

Abstract translation: 一种装置用于测量被测器件的互调失真的特性参数。 该布置可以包括在不同测试频率下的至少两个音调的发生器，以及衰减路径，该衰减路径将该设备的复制品馈送到等于设备增益的因子。 该装置还可以包括用于在由设备输出的信号和两个音调之间产生差分信号的电路，以及具有差分信号的电路输入并测量作为其功能的特性参数。

公开(公告)号：US20060250099A1

公开(公告)日：2006-11-09

申请号：US11381432

申请日：2006-05-03

Applicant: Giuseppe Maiocchi ,  Ezio Galbiati ,  Michele Boscolo

Inventor： Giuseppe Maiocchi ,  Ezio Galbiati ,  Michele Boscolo

IPC: H02P25/12

CPC classification number: H02P6/182 ,  H02P25/034

Abstract: A method for sensing a back electromotive force induced in a winding of a voice coil electro-mechanical actuator controlled in a discontinuous mode by alternating conduction phases to off-phases includes sensing voltage at terminals of the winding during an off-phase The winding is driven during a conduction phase immediately preceding the off-phase to invert, during a final portion of the conduction phase before entering an off-phase, a direction of flow of the current through the winding.

Abstract translation: 用于感测在不连续模式下控制的音圈机电致动器的绕组中感应到的反电动势的方法是通过将导通相交替为非相，包括在断相期间感测绕组端子处的电压。绕组被驱动 在紧邻异相之前的导通阶段期间，在进入截止相之前的导通阶段的最后部分期间，电流通过绕组的流动方向。

公开(公告)号：US20060246712A1

公开(公告)日：2006-11-02

申请号：US11312231

申请日：2005-12-19

Applicant: Yudong Kim ,  Ilya Karpov ,  Charles Kuo ,  Greg Atwood ,  Maria Marangon ,  Tyler Lowrey

Inventor： Yudong Kim ,  Ilya Karpov ,  Charles Kuo ,  Greg Atwood ,  Maria Marangon ,  Tyler Lowrey

IPC: H01L21/4763

CPC classification number: H01L45/16 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/1683

Abstract: A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.

公开(公告)号：US20060239076A1

公开(公告)日：2006-10-26

申请号：US11279385

申请日：2006-04-11

Applicant: Luigi Pascucci ,  Paolo Rolandi

Inventor： Luigi Pascucci ,  Paolo Rolandi

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

Abstract: A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract translation: 非易失性存储器电子器件集成在半导体上，并且具有闪存EEPROM类型，其具有NAND架构，其包括分成物理扇区的至少一个存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列或 位线的存储单元。 给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端 行指向源行的相同选择行。

公开(公告)号：US20060208719A1

公开(公告)日：2006-09-21

申请号：US11360003

申请日：2006-02-22

Applicant: Fabrizio Librizzi

Inventor： Fabrizio Librizzi

IPC: G05F1/00

CPC classification number: H02M3/33561 ,  H02M3/33576

Abstract: A control circuit for a pulsed width modulation controller includes a main controlled switch to selectively block an energization signal from a switched mode power supply and a free-wheeling synchronous switch for selectively transferring the energization signal as an output signal. The controller also includes a control circuit that includes: a PWM module having an input terminal, for connection with the switched mode power supply, and a PWM comparator; a drive circuit for the main controlled switch controlled by the PWM comparator; a low-side drive circuit for the free-wheeling synchronous switch controlled by the PWM comparator; and a ramp generator having a synchronization terminal connected to the power supply and a comparator sensing the signal on the synchronization terminal. The ramp signal from the ramp generator defines the threshold of the PWM comparator to thereby control operation of the drive circuits.

Abstract translation: 用于脉冲宽度调制控制器的控制电路包括主控制开关，用于选择性地阻断来自开关模式电源的通电信号和用于选择性地传送通电信号作为输出信号的续流同步开关。 控制器还包括一个控制电路，它包括：具有用于与开关模式电源连接的输入端的PWM模块和一个PWM比较器; 由PWM比较器控制的主控开关的驱动电路; 用于由PWM比较器控制的续流同步开关的低侧驱动电路; 以及具有连接到电源的同步端子和感测同步端子上的信号的比较器的斜坡发生器。 来自斜坡发生器的斜坡信号定义PWM比较器的阈值，从而控制驱动电路的操作。

公开(公告)号：US20060161825A1

公开(公告)日：2006-07-20

申请号：US11304488

申请日：2005-12-15

Applicant: Guido Lomazzi ,  Ilaria Renna ,  Marco Maccarone

Inventor： Guido Lomazzi ,  Ilaria Renna ,  Marco Maccarone

IPC: G11C29/00

CPC classification number: G11C29/1201 ,  G11C16/04 ,  G11C29/006 ,  G11C29/16 ,  G11C29/46 ,  G11C2029/2602

Abstract: A non-volatile memory device includes a chip of semiconductor material. The chip includes a memory and control means for performing a programming operation, an erasing operation and a reading operation on the memory in response to corresponding external commands. The chip further includes testing means for performing at least one test process including the repetition of at least one of said operations by the control means, and a single access element for enabling the testing means.

Abstract translation: 非易失性存储器件包括半导体材料芯片。 芯片包括用于响应于相应的外部命令对存储器执行编程操作，擦除操作和读取操作的存储器和控制装置。 该芯片还包括用于执行至少一个测试过程的测试装置，该测试过程包括由控制装置重复所述操作中的至少一个，以及用于启用测试装置的单个访问元件。

公开(公告)号：US20060158946A1

公开(公告)日：2006-07-20

申请号：US11261901

申请日：2005-10-28

Applicant: Alberto Taddeo

Inventor： Alberto Taddeo

IPC: G11C7/02

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C2207/063

Abstract: A current sense amplifier, in particular for low voltage applications, of the type incorporated in a memory electronic device and including a differential amplifier having inputs respectively associated with a matrix circuit leg, connected to a cell to be sensed, and a reference circuit leg, connected a reference cell. At least the matrix circuit leg has a first MOS transistor to which an inverter is connected in a cascode configuration and a first input of the differential amplifier corresponding to the matrix circuit leg is coupled to a conduction terminal of the first MOS transistor and to the bitline of the memory matrix by a second MOS transistor.

Abstract translation: 特别是用于低电压应用的电流读出放大器，其结合在存储器电子器件中并且包括具有分别与连接到要感测的单元的矩阵电路支路的输入和参考电路支路的差分放大器， 连接参考单元。 至少矩阵电路支路具有第一MOS晶体管，逆变器以共源共栅配置连接到该第一MOS晶体管，并且与矩阵电路支路对应的差分放大器的第一输入端耦合到第一MOS晶体管的导通端和位线 的第二MOS晶体管的存储矩阵。

公开(公告)号：US20060134821A1

公开(公告)日：2006-06-22

申请号：US11343400

申请日：2006-01-31

Applicant: Chantal Combi ,  Benedetto Vigna

Inventor： Chantal Combi ,  Benedetto Vigna

IPC: H01L21/00

CPC classification number: H01H59/0009

Abstract: The method for manufacturing a micromechanical switch includes manufacturing a hanging bar, on a first semiconductor substrate, equipped at an end thereof with a contact electrode, and a frame projecting from the first semiconductor substrate. A second semiconductor substrate with conductive tracks includes a second input/output electrode and a third starting electrode, and first and second spacers electrically connected to the conductive tracks. The frame is abutted with the first spacers so that the fourth contact electrode abuts on the second input/output electrode in response to an electrical signal provided to the hanging bar by the third starting electrode.

公开(公告)号：US20060098732A1

公开(公告)日：2006-05-11

申请号：US11267077

申请日：2005-11-04

Applicant: Arcangelo Bruna ,  Luca Celetto

Inventor： Arcangelo Bruna ,  Luca Celetto

IPC: H04N11/04 ,  H04B1/66 ,  H04N7/12 ,  H04N11/02

CPC classification number: H04N19/124 ,  H04N19/137 ,  H04N19/14 ,  H04N19/176 ,  H04N19/194 ,  H04N19/45 ,  H04N19/61

Abstract: The method for block coding data, such as video data, via a compression operation includes applying to input-data blocks a discrete-cosine-transform (DCT) operation and a quantization operation to produce compressed-data blocks. The compressed-data blocks are subjected to a coding operation to obtain compressed output flows; and an inverse-quantization operation and an inverse-discrete-cosine-transform (IDCT) operation are applied on the compressed-data blocks to obtain reconstructed blocks. The method includes controlling generation of mismatch errors from the input-data blocks by detecting data blocks from the input-data blocks and compressed-data blocks that are liable to cause mismatch errors, and modifying the blocks that are liable to cause mismatch errors prior to the coding operation.

Abstract translation: 用于通过压缩操作对数据（诸如视频数据）进行数据块编码的方法包括：向输入数据块应用离散余弦变换（DCT）操作和量化操作以产生压缩数据块。 对压缩数据块进行编码操作以获得压缩的输出流; 并且在压缩数据块上应用逆量化操作和逆离散余弦变换（IDCT）操作以获得重构块。 该方法包括通过检测来自输入数据块的数据块和容易引起不匹配错误的压缩数据块来控制来自输入数据块的失配错误的产生，以及修改易于引起不匹配错误的块， 编码操作。

公开(公告)号：US20060063352A1

公开(公告)日：2006-03-23

申请号：US11225883

申请日：2005-09-13

Applicant: Gabriele Barlocchi ,  Flavio Villa

Inventor： Gabriele Barlocchi ,  Flavio Villa

IPC: H01L21/30 ,  H01L21/20

CPC classification number: H01L21/3247 ,  H01L21/3043 ,  H01L21/76251 ,  H01L21/76259

Abstract: A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.

Abstract translation: 一种工艺使用半导体处理技术制造晶片。 在第一晶片的顶表面上形成接合层; 在属于第二晶片的半导体材料的衬底中挖出深沟槽。 半导体材料的顶层形成在衬底的顶部上，以封闭顶部的深沟槽并形成至少一个埋入空腔。 第二晶片的顶层通过结合层结合到第一晶片。 对这两个晶片进行热处理，其导致顶层的至少一部分与第一晶片的接合和掩埋腔的加宽。 以这种方式，将结合到第一晶片的顶层的部分与第二晶片的其余部分分离，以形成复合晶片。