公开(公告)号：US10164029B2

公开(公告)日：2018-12-25

申请号：US14987598

申请日：2016-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/417 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

公开(公告)号：US10163912B2

公开(公告)日：2018-12-25

申请号：US15286795

申请日：2016-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L27/11 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/165 ,  H01L27/11582 ,  H01L49/02

Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.

公开(公告)号：US20180350813A1

公开(公告)日：2018-12-06

申请号：US16041996

申请日：2018-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

公开(公告)号：US10134669B2

公开(公告)日：2018-11-20

申请号：US15911617

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion. The upper portion and the lower portion each have a constant width, and the middle portion has a tapered width which is gradually tapered from the upper portion to the lower portion.

公开(公告)号：US20180315754A1

公开(公告)日：2018-11-01

申请号：US16022713

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US09935103B2

公开(公告)日：2018-04-03

申请号：US15392693

申请日：2016-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device includes first and second Fin FET and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section a maximum width of the separation plug is located at a height Hb, which is less than ¾ of a height Ha of the separation plug.

公开(公告)号：US09929242B2

公开(公告)日：2018-03-27

申请号：US14749602

申请日：2015-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/423 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/42376 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.

公开(公告)号：US20180019342A1

公开(公告)日：2018-01-18

申请号：US15715153

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/785

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US20180005877A1

公开(公告)日：2018-01-04

申请号：US15701416

申请日：2017-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/76834 ,  H01L21/02123 ,  H01L21/76802 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are provided. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a spacer, a first dielectric layer, a shielding layer and a connector. The first gate stack is over the substrate. The spacer is disposed on and contacted to at least one sidewall of the first gate stack. The first dielectric layer is aside the spacer. The shielding layer covers a top surface of the spacer and a top surface of the first dielectric layer. The connector contacts a portion of a top surface of the first gate stack.

公开(公告)号：US09837510B2

公开(公告)日：2017-12-05

申请号：US15298462

申请日：2016-10-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.