公开(公告)号：US06002173A

公开(公告)日：1999-12-14

申请号：US995747

申请日：1992-12-21

Applicant: Paolo Casati ,  Pierangelo Magni ,  Giuseppe Marchisi

Inventor： Paolo Casati ,  Pierangelo Magni ,  Giuseppe Marchisi

IPC: H01L23/28 ,  H01L23/29 ,  H01L23/433 ,  H01L23/50 ,  H01L23/48 ,  H01L23/10

CPC classification number: H01L23/4334 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/181

Abstract: A structure is disclosed which comprises a metal plate, a chip of a semiconductor material attached to the plate, terminal leads, interconnection wires between the leads and the metallized regions of the chip, and a polymer body encapsulating all this with the exception of a surface of the plate and part of the leads. To achieve improved bond between the polymer and the metal, predetermined areas of the plate and the leads have a higher roughness than 1 (R.sub.a .gtoreq.1 .mu.m).

Abstract translation: 公开了一种结构，其包括金属板，连接到板的半导体材料的芯片，端子引线，引线之间的互连线和芯片的金属化区域，以及除了表面之外封装所有这些的聚合物体 的板和部分引线。 为了实现聚合物和金属之间的改善的接合，板的预定区域和引线具有比1（Ra> / =1μm）更高的粗糙度。

公开(公告)号：US6000980A

公开(公告)日：1999-12-14

申请号：US807113

申请日：1996-12-13

Applicant: Livio Baldi ,  Alessandro Tonti

Inventor： Livio Baldi ,  Alessandro Tonti

IPC: H01J9/02

CPC classification number: H01J9/025 ,  H01J2201/319

Abstract: A process for forming a microtip cathode structure on a field emission display panel which avoids the need of vacuum depositing a lift-off layer for the microtip deposition overstructure in specially equipped reactors to accomplish a deposition at a grazing angle, by co-patterening the lift-off layer together with an underlying metal grid layer using a succession of different etching steps through the openings of a grid definition mask. According to an embodiment, nickel is used as lift-off material and is either wet-etched or sputter-etched before performing a plasma etch of the underlying grid metal layer. According to an alternative embodiment, the masking resist layer is used as lift-off material.

Abstract translation: 一种用于在场发射显示面板上形成微尖端阴极结构的方法，其避免真空沉积用于特别装备的反应器中的微尖端沉积过度结构的剥离层，以通过共同观察电梯来实现放电角度的沉积 使用一系列不同的蚀刻步骤通过网格定义掩模的开口与底层金属网格层一起使用。 根据一个实施例，镍用作剥离材料，并且在对下面的栅格金属层进行等离子体蚀刻之前被湿式蚀刻或溅射蚀刻。 根据替代实施例，掩模抗蚀剂层用作剥离材料。

公开(公告)号：US5994948A

公开(公告)日：1999-11-30

申请号：US921930

申请日：1997-08-27

Applicant: Simone Bartoli ,  Antonio Russo ,  Mauro Luigi Sali

Inventor： Simone Bartoli ,  Antonio Russo ,  Mauro Luigi Sali

IPC: G11C16/30 ,  G05F1/10

CPC classification number: G11C16/30

Abstract: A CMOS twin-tub negative voltage switching architecture is for a non-volatile memory device and includes a negative voltage multiplier for generating a increased voltage value starting from a single main power supply. A voltage regulator feedback is connected to the voltage multiplier for regulating the generated negative voltage value; and a plurality of independent switch circuits each one receiving as an input the negative voltage value and producing as an output a predetermined local negative voltage.

Abstract translation: CMOS双槽负电压开关结构用于非易失性存储器件，并且包括用于从单个主电源开始产生增加的电压值的负电压倍增器。 电压调节器反馈连接到电压倍增器，用于调节产生的负电压值; 以及多个独立的开关电路，每个独立的开关电路每个接收负电压值作为输入，并产生预定的局部负电压作为输出。

公开(公告)号：US5990748A

公开(公告)日：1999-11-23

申请号：US129288

申请日：1998-08-05

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

IPC: H03F1/08 ,  H03F1/14 ,  H03F1/34

CPC classification number: H03F1/086

Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage and an amplifier output stage connected serially together to receive an input signal on at least one input terminal of the amplifier and generate an amplified signal on an output terminal of the amplifier. Provided between the input and output stages is an intermediate node which is connected to a compensation block to receive a frequency-variable compensation signal therefrom. The compensation block is coupled with its input to the input terminal of the amplifier. The compensation block is connected to receive at least the feedback signal. Preferably, the compensation signal is variable as a function of a gain value which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value.

Abstract translation: 相对于闭环增益自补偿的运算放大器频率包括跨导输入级和串联连接的放大器输出级，以在放大器的至少一个输入端上接收输入信号，并在输出端产生放大信号 的放大器。 在输入级和输出级之间设置有中间节点，其连接到补偿块以从其接收频率可变的补偿信号。 补偿块与其输入耦合到放大器的输入端。 补偿块被连接以至少接收反馈信号。 优选地，补偿信号作为由反馈电路确定的增益值的函数而变化，并且补偿信号的所述变化以与增益值成反比关系的关系发生。

公开(公告)号：US5977591A

公开(公告)日：1999-11-02

申请号：US824888

申请日：1997-03-18

Applicant: Lorenzo Fratin ,  Carlo Riva

Inventor： Lorenzo Fratin ,  Carlo Riva

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/4983 ,  H01L21/28105 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7836

Abstract: A MOS transistor capable of withstanding relatively high voltages is of a type integrated on a region included in a substrate of semiconductor material, having conductivity of a first type and comprising a channel region intermediate between a first active region of source and a second active region of drain. Both these source and drain regions have conductivity of a second type and extend from a first surface of the substrate. The transistor also has a gate which includes at least a first polysilicon layer overlying the first surface of at least the channel region, to which it is coupled capacitively through a gate oxide layer. According to the invention, the first polysilicon layer includes a mid-portion which only overlies the channel region and has a first total conductivity of the first type, and a peripheral portion with a second total conductivity differentiated from the first total conductivity. The peripheral portion partly overlies the source and drain active regions toward the channel region.

Abstract translation: 能够承受相对高电压的MOS晶体管是集成在包括在半导体材料的衬底中的区域上的类型，其具有第一类型的导电性并且包括在源的第一有源区和第二有源区之间的沟道区 排水。 这些源极和漏极区都具有第二类型的导电性并且从衬底的第一表面延伸。 晶体管还具有栅极，该栅极至少包括覆盖至少沟道区的第一表面的第一多晶硅层，其通过栅极氧化物层电容耦合到该栅极氧化物层。 根据本发明，第一多晶硅层包括仅覆盖沟道区并具有第一类型的第一总电导率的中间部分，以及与第一总电导率不同的具有第二总电导率的外围部分。 外围部分部分地覆盖源极和漏极有源区域朝向沟道区域。

公开(公告)号：US5976933A

公开(公告)日：1999-11-02

申请号：US897799

申请日：1997-07-21

Applicant: Claudio Brambilla ,  Manlio Sergio Cereda ,  Giancarlo Ginami

Inventor： Claudio Brambilla ,  Manlio Sergio Cereda ,  Giancarlo Ginami

IPC: H01L21/8247 ,  H01L23/528 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L23/5283 ,  H01L27/115 ,  H01L27/11543 ,  H01L27/105 ,  H01L2924/0002

Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD) said, first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

Abstract translation: 一种用于制造集成电路的方法，该集成电路包括存储单元阵列，提供：a）在半导体层（6）的存储单元阵列区域中形成用于存储单元的有效区域; b）在所述存储单元的所述有源区上形成栅极氧化物层（8）; c）在整个集成电路上形成第一层导电材料（9）; d）在第一层导电材料（9）上形成一层绝缘材料（10）; e）从存储单元阵列区域的外部去除绝缘材料层（10）; f）在整个集成电路上形成第二层导电材料（11），其在存储单元阵列区域中通过绝缘材料层（10）与第一导电材料层（9）分离，而在存储单元外部 阵列区域直接叠加在所述第一导电材料层（9）上; g）在存储单元阵列区域内部，限定用于形成存储单元阵列（1）的行（3）的第二导电材料层（11）的第一条带（22），以及限定第二条带 用于形成用于将存储单元阵列的行（3）与电路（5，RD）电互连的互连线（100）的第二导电材料层（11）的第一层（17），所述第一条带（22）和 第二导电材料层（11）的第二条带（17）在其边界区域的各自端部自动连接。

公开(公告)号：US5973537A

公开(公告)日：1999-10-26

申请号：US948986

申请日：1997-10-10

Applicant: Andrea Baschirotto ,  Angelo Nagari ,  Rinaldo Castello

Inventor： Andrea Baschirotto ,  Angelo Nagari ,  Rinaldo Castello

IPC: H03F3/00 ,  H03F3/45 ,  H03K5/00

CPC classification number: H03F3/005 ,  H03F3/45946 ,  H03F2203/45421

Abstract: In switch-capacitor systems for extremely low supply voltage, employing a fully differential switched op-amp, proper functioning of nMOS switches coupled to the inverting input node of an integrated stage capable of outputting a common mode control signal is made possible by retaining the ground potential on the input node to prevent body effects on the threshold of nMOS switches by means of an auxiliary switched capacitor.

Abstract translation: 在采用完全差分开关运算放大器的开关电容器系统中，通过使用完全差分开关运算放大器，可以通过保持接地来实现耦合到能够输出共模控制信号的集成级的反相输入节点的正常功能 输入节点上的电位，以通过辅助开关电容器来防止身体对nMOS开关阈值的影响。

公开(公告)号：US5963407A

公开(公告)日：1999-10-05

申请号：US020420

申请日：1998-02-09

Applicant: Leonardo Fragapane ,  Romeo Letor

Inventor： Leonardo Fragapane ,  Romeo Letor

IPC: H03K17/082 ,  H02H3/00

CPC classification number: H03K17/0822 ,  H03K17/0828

Abstract: A fast operating, electronic overvoltage protection device intended for a power transistor having at least one control terminal of the MOS type is disclosed. The device comprises a Zener diode associated with the power transistor and integrated together therewith in a semiconductor substrate, and a second transistor connected to the power transistor into a Darlington configuration and also connected to the Zener diode. The protection from overvoltages provided by the device is very fast in operation, and can be implemented in integrated form at reduced cost and without introducing parasitic elements.

Abstract translation: 公开了一种用于具有MOS类型的至少一个控制端的功率晶体管的快速操作的电子过电压保护装置。 该器件包括与功率晶体管相关并且与半导体衬底集成在一起的齐纳二极管，以及连接到功率晶体管为达林顿配置并且还连接到齐纳二极管的第二晶体管。 由器件提供的过电压保护在操作上非常快速，并且可以以降低成本并且不引入寄生元件的集成形式来实现。

公开(公告)号：US5959917A

公开(公告)日：1999-09-28

申请号：US819519

申请日：1997-03-17

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C15/04 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/789 ,  G11C15/046

Abstract: A circuit for detecting the coincidence between a binary information unit stored therein and an external datum comprises at least one programmable memory element, a sensing circuit for reading a datum stored in the programmable memory element and a digital comparator for comparing the datum stored in the programmable memory element with the external datum. The sensing circuit comprises a bistable latch having at least one set input coupled to the programmable memory element and an output suitable to take either one of two logic levels according to a programming state of the programmable memory element, the output supplying directly the digital comparator.

Abstract translation: 用于检测存储在其中的二进制信息单元与外部数据之间的一致性的电路包括至少一个可编程存储器元件，用于读取存储在可编程存储器元件中的数据的感测电路和用于比较存储在可编程存储元件中的数据的数字比较器 内存元素与外部数据。 感测电路包括双稳态锁存器，其具有耦合到可编程存储器元件的至少一个设置输入端和适于根据可编程存储器元件的编程状态采用两个逻辑电平中的任一个的输出，该输出直接提供给数字比较器。

公开(公告)号：US5943000A

公开(公告)日：1999-08-24

申请号：US956273

申请日：1997-10-22

Applicant: Maurizio Nessi ,  Rinaldo Castello ,  Giona Fucili ,  Marcello Leone ,  Annamaria Rossi

Inventor： Maurizio Nessi ,  Rinaldo Castello ,  Giona Fucili ,  Marcello Leone ,  Annamaria Rossi

IPC: H03M1/06 ,  H03M1/68 ,  H03M1/76 ,  H03M1/78

CPC classification number: H03M1/682 ,  H03M1/0602 ,  H03M1/765

Abstract: A digital-to-analog converter includes a potentiometric string suitable for realizing a relatively high number of bits that significantly reduces the silicon area requirement and simplifies mismatch compensation. The structure includes a first resistance string to realize a first DAC to convert a first number of most significative bits, and a second potentiometric string functionally connected in cascade to the first, but realized with MOS transistors. The structure of the invention allows the coupling of the two DACs in cascade by exploiting the MOS transistors that form the second potentiometric string, that is, the second DAC, thus avoiding the use of operational switches or amplifiers which may provide error sources. Moreover, the structure of the invention lends itself to the implementation of efficient compensation circuits for integral and differential linearity errors.

Abstract translation: 数模转换器包括适于实现相对较高数量的位的电位串，其显着地降低了硅面积需求并简化了不匹配补偿。 该结构包括第一电阻串，以实现第一DAC以转换第一数量最有意义的位，以及第二电位串，其功能上串联连接到第一电位，但是用MOS晶体管实现。 本发明的结构允许通过利用形成第二电位串的MOS晶体管（即第二DAC）级联耦合两个DAC，从而避免使用可能提供误差源的操作开关或放大器。 此外，本发明的结构适用于实现用于积分和微分线性误差的有效补偿电路。