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公开(公告)号：US20240387499A1
公开(公告)日：2024-11-21
申请号：US18787831
申请日：2024-07-29
Applicant: Micron Technology, Inc.
Inventor： Jong Sik Paek , Yeongbeom Ko
IPC: H01L25/18 , H01L23/00 , H01L23/498 , H01L25/00
Abstract: Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.
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362.发明申请公开(公告)号：US20240386929A1
公开(公告)日：2024-11-21
申请号：US18786234
申请日：2024-07-26
Applicant: Micron Technology, Inc.
Inventor： Andrea D'alessandro , Violante Moschiano , Giacomo Donati , Luigi Marchese
Abstract: A microelectronic device comprises a microelectronic device structure comprising a section comprising page buffers, and an additional section horizontally neighboring the section and comprising page buffer drivers and a timing delay chain coupled to the page buffer drivers. Each of the page buffer drivers is coupled to different group of the page buffers than each other of the page buffer drivers. The timing delay chain comprises timing delay circuits coupled in series with one another. Each of the timing delay circuits is configured to adjustably delay propagation of a control signal therethrough. Memory devices, methods of operating memory devices, and electronic systems are also described.
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公开(公告)号：US20240385961A1
公开(公告)日：2024-11-21
申请号：US18664142
申请日：2024-05-14
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer
IPC: G06F12/02 , G06F12/0891
Abstract: Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.
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公开(公告)号：US20240385926A1
公开(公告)日：2024-11-21
申请号：US18661526
申请日：2024-05-10
Applicant: Micron Technology, Inc.
Inventor： Steven Michael Kientz , Hyungseok Kim , Zixiang Loh , Patrick R. Khayat , Jun Wan
Abstract: A system having a processing device operatively coupled with a memory device to perform the following operations: responsive to detecting a triggering event, measuring a temperature of the memory device to obtain a suspend temperature value, enabling a suspend temperature flag to indicate that temperature input for a step of an error handling operation is based on the suspend temperature value. Updating an operating temperature with the suspend temperature value. Determining, using a data structure which maps temperatures to read level offsets, a read level offset for the step of the error handling operation, based on the operating temperature. Causing the step of the error handling operation to be performed on a set of cells using a read level value based on the read level offset and a base read level, an disabling the suspend temperature flag.
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365.发明申请公开(公告)号：US20240385713A1
公开(公告)日：2024-11-21
申请号：US18787322
申请日：2024-07-29
Applicant: Micron Technology, Inc.
Inventor： Pankaj Sharma
IPC: G06F3/041 , G06F3/01 , G06F3/0481 , G06F3/04817 , G06F3/0482 , G06F3/0484 , G06F3/04883 , G06F3/04886 , G06Q10/10 , G11B27/10 , H01L29/24 , H01L29/423 , H01L29/78 , H01L29/788 , H04L65/403 , H04N21/00 , H04N21/472 , H04N21/84 , H04N21/854
Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.
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Patent Agency Ranking
公开(公告)号：US20240385645A1
公开(公告)日：2024-11-21
申请号：US18659991
申请日：2024-05-09
Applicant: Micron Technology, Inc.
Inventor： Martin Brox
IPC: G06F1/12
Abstract: Methods, systems, and devices for latency synchronization are described. A memory device may receive a data clock signal having a first rate and may generate a second clock signal having a second rate based on the data clock signal. A sampler may sample a first command signal indicating a command, where the second clock signal includes a first delay. A synchronizer may receive a second command signal from the sampler and a third clock signal from the sampler, where the second command signal and the third clock signal include a second delay. The synchronizer may synchronize a first timing of the second clock signal with a second timing of the third clock signal based on receiving the second command signal and the third clock signal and may output a signal including the second command signal and a synchronized clock signal having the second rate based on the synchronization.
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公开(公告)号：US12149609B2
公开(公告)日：2024-11-19
申请号：US17686713
申请日：2022-03-04
Applicant: Micron Technology, Inc.
Inventor： Alberto Troia , Antonino Mondello
Abstract: Techniques for calculating a hash value of a single secure array of memory blocks in a sequential set of dice. The array can be defined by a set of address-size pairs. Each pair provides a pointer by including an address of a memory block and a size of the block. The hash value can be calculated by: for each die that is not the last die, partially applying a hash function, without final padding, to the memory blocks of the secure array in the die to generate a partial digest. And, for the last die, fully applying the hash function, with the final padding, to the memory blocks of the secure array in the last die to generate the hash value of the secure array, which can include adding an accumulation of partial digests to data from the last die as a basis for the generation of the hash value.
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公开(公告)号：US12148483B2
公开(公告)日：2024-11-19
申请号：US18539798
申请日：2023-12-14
Applicant: Micron Technology, Inc.
Inventor： Agostino Macerola , Gianni Rea
Abstract: A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.
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公开(公告)号：US12147689B2
公开(公告)日：2024-11-19
申请号：US18229795
申请日：2023-08-03
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Ying Yu Tai
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on temperature-related memory component capabilities. The controller can obtain a write temperature associated with an individual group of memory components. Based on the write temperature and a temperature threshold associated with the individual group of memory components, the controller can select an individual media management operation to perform.
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公开(公告)号：US20240381781A1
公开(公告)日：2024-11-14
申请号：US18782478
申请日：2024-07-24
Applicant: Micron Technology, Inc.
Inventor： Gurtej S. Sandhu , Sumeet C. Pandey
Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attractor species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attractor species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.
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