公开(公告)号：US10163914B2

公开(公告)日：2018-12-25

申请号：US15603827

申请日：2017-05-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

IPC: H01L29/66 ,  H01L27/11

Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.

公开(公告)号：US20180366470A1

公开(公告)日：2018-12-20

申请号：US16114596

申请日：2018-08-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Hui Zang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L23/535 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

公开(公告)号：US20180366461A1

公开(公告)日：2018-12-20

申请号：US15627835

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Haiting Wang ,  Daniel Jaeger

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0207 ,  H01L28/20 ,  H01L28/24 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.

公开(公告)号：US10128187B2

公开(公告)日：2018-11-13

申请号：US15206361

申请日：2016-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts

IPC: H01L21/70 ,  H01L23/528 ,  H01L21/768 ,  H01L23/535 ,  H01L23/66 ,  H01L29/06 ,  H01L29/78

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack.

公开(公告)号：US10121893B2

公开(公告)日：2018-11-06

申请号：US15797634

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred J Eller ,  Min-Hwa Chi ,  Jerome J. B. Ciavatti

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/49 ,  H01L27/11

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

公开(公告)号：US10115738B2

公开(公告)日：2018-10-30

申请号：US15354205

申请日：2016-11-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned back-plane and well contacts for a fully depleted silicon on insulator device and methods of manufacture. The structure includes a back-plane, a p-well and an n-well formed within a bulk substrate; a contact extending from each of the back-plane, the p-well and the n-well; a gate structure formed above the back-plane, the p-well and the n-well; and an insulating spacer isolating the contact of the back-plane from the gate structure.

公开(公告)号：US10103247B1

公开(公告)日：2018-10-16

申请号：US15785631

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/45 ,  H01L21/8234

Abstract: Methods form a structure having a lower source/drain contacting a substrate at the bottom of a transistor. A semiconductor fin extends from the lower source/drain away from the bottom of the transistor. An upper source/drain contacts an opposite end of the fin at the top of the transistor. A gate conductor surrounds (but is electrically insulated from the fin) and includes a raised contact portion extending toward the top of the transistor. A buried contact is located at the bottom of the transistor, and is electrically connected to the first source/drain. A silicide and a conformal metal are between the buried contact and the first source/drain. The conformal metal is also between the gate conductor and the fin. A first contact extends to the buried contact, a second contact extends to the upper source/drain, and a third contact extends to the raised contact portion.

公开(公告)号：US10096604B2

公开(公告)日：2018-10-09

申请号：US15259472

申请日：2016-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Hui Zang

IPC: H01L27/11 ,  H01L23/535 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

公开(公告)号：US10090204B1

公开(公告)日：2018-10-02

申请号：US15609201

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jae Gon Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L23/535

Abstract: The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a set of fins within an ILD layer on a substrate; a first gate dielectric over the substrate and extending along opposing sidewalls of each fin in the set of fins, a metal stack adjacent to the first gate dielectric and on the opposing sidewalls of each fin, the metal stack having a first portion over the substrate and a second portion contacting the first gate dielectric and extending along the opposing sidewalls of each fin, wherein at least the first portion of the metal stack and a portion of the first gate dielectric above the substrate is replaced by another dielectric material; a set of epitaxial regions within the ILD layer; and a conductor within the ILD layer and extending over each epitaxial region.

公开(公告)号：US10090169B1

公开(公告)日：2018-10-02

申请号：US15475272

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/321 ,  H01L29/49 ,  H01L21/3105

Abstract: The disclosure is directed to methods of forming an integrated circuit structure. One method may include: forming a metal gate within a dielectric layer over a substrate; forming an opening within the metal gate; recessing the metal gate such that a height of the metal gate is reduced; forming an insulator over the recessed metal gate and filling the opening; and planarizing the insulator to a top surface of the dielectric layer.