公开(公告)号：US06974739B2

公开(公告)日：2005-12-13

申请号：US10440005

申请日：2003-05-16

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/768 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/8238

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11546

Abstract: A gate dielectric (150) for a gate (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate (140). The dielectric thickness on the other gate is controlled by the dopant concentration in the other gate. The gates may be gates of different MOS transistors, or a select gate and a floating gate of a memory cell. Other features are also provided.

Abstract translation: 用于栅极（160）的栅极电介质（150）通过热氧化同时作为另一栅极（140）的表面上的电介质形成。 另一个栅极上的电介质厚度由另一个栅极中的掺杂剂浓度控制。 栅极可以是不同MOS晶体管的栅极，或存储单元的选择栅极和浮置栅极。 还提供其他功能。

公开(公告)号：US06924241B2

公开(公告)日：2005-08-02

申请号：US10373917

申请日：2003-02-24

Applicant: Tai-Peng Lee

Inventor： Tai-Peng Lee

IPC: H01L21/318 ,  H01L21/336 ,  H01L29/20 ,  H01L21/31

CPC classification number: H01L29/66825 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3185 ,  H01L29/2003 ,  Y10S439/952

Abstract: A method for producing an ultraviolet light (UV) transmissive silicon nitride layer in a plasma enhanced chemical vapor deposition (PECVD) reactor is presented. The UV transmissive film is produced by reducing, in comparison to a standard silicon nitride process, a flow rate of the silane and ammonia gas precursors to the PECVD reactor, and significantly increasing a flow rate of nitrogen gas to the reactor. The process reduces the concentration of Si—H bonds in the silicon nitride film to provide UV transmissivity. Further, the amount of nitrogen in the film is greater than in a standard PECVD silicon nitride film, and as a percentage constitutes a greater part of the film than silicon. The film has excellent step coverage and a low number of pinhole defects. The film may be used as a passivation layer in a UV erasable memory integrated circuit.

Abstract translation: 提出了一种在等离子体增强化学气相沉积（PECVD）反应器中制造紫外光（UV）透射氮化硅层的方法。 与标准氮化硅工艺相比，通过将硅烷和氨气前体的流量减少到PECVD反应器，并且显着增加氮气流向反应器的方式，来制备UV透射膜。 该方法降低了氮化硅膜中Si-H键的浓度以提供UV透射率。 此外，膜中的氮的量大于标准PECVD氮化硅膜中的氮量，并且作为百分比构成比硅的更大部分的膜。 该片具有优异的台阶覆盖率和较少的针孔缺陷。 该膜可用作UV可擦除存储器集成电路中的钝化层。

公开(公告)号：US20050139889A1

公开(公告)日：2005-06-30

申请号：US11062563

申请日：2005-02-23

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/336 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/10888 ,  H01L27/10832 ,  H01L27/10861 ,  H01L29/945

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

公开(公告)号：US20050127453A1

公开(公告)日：2005-06-16

申请号：US11041503

申请日：2005-01-21

Applicant: Ming-Sheng Tung ,  Yueh-Chuan Lee

Inventor： Ming-Sheng Tung ,  Yueh-Chuan Lee

IPC: H01L21/336 ,  H01L21/60 ,  H01L23/485 ,  H01L21/8242 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

Abstract translation: 用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

公开(公告)号：US20050079681A1

公开(公告)日：2005-04-14

申请号：US10967181

申请日：2004-10-19

Applicant: Yueh-Chuan Lee ,  Shih-Lung Chen

Inventor： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC: H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/20

CPC classification number: H01L27/1087 ,  H01L29/66181 ,  H01L29/945 ,  Y10S438/923

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract translation: 一种制造沟槽电容器的方法，包括提供半导体衬底，在衬底中形成深沟槽，在沟槽的表面上形成薄的牺牲层，以及在薄牺牲层上形成半球状硅晶粒层，其中牺牲层 层的厚度在随后的步骤中用作蚀刻停止以去除半球状硅晶粒层的至少一部分，并且是导电的。

公开(公告)号：US20050079427A1

公开(公告)日：2005-04-14

申请号：US10957678

申请日：2004-10-05

Applicant: Brian Lee ,  Chih-Yu Lee

Inventor： Brian Lee ,  Chih-Yu Lee

IPC: G03C5/00 ,  G03F1/00 ,  G03F9/00 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/32139 ,  G03F1/30 ,  H01L27/10861 ,  H01L27/10891

Abstract: An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.

公开(公告)号：US06875653B2

公开(公告)日：2005-04-05

申请号：US10210031

申请日：2002-08-02

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10832 ,  H01L27/0207 ,  H01L27/10867 ,  H01L27/10888

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract translation: 一种存储器件，包括半导体衬底和存储器单元阵列，每个单元与相邻单元电隔离并且包括由衬底形成的岛，所述岛具有顶部部分和至少一个侧壁部分，并且间隔开 通过基板上的底面从其他岛形成与该侧壁部分相邻的电容器，以及形成在该岛的顶部的晶体管，该晶体管包括形成于顶部表面的栅极氧化层，栅极 形成在栅极氧化物层上，以及形成在顶部的第一和第二扩散区域，第一扩散区域与第二扩散区域间隔开。

公开(公告)号：US20050062090A1

公开(公告)日：2005-03-24

申请号：US10965160

申请日：2004-10-15

Applicant: Yu-Ying Lian

Inventor： Yu-Ying Lian

IPC: H01G4/228 ,  H01L21/02 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L28/91 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L29/66181

Abstract: A trench capacitor includes an electrode having a first conductive area formed in a trench provided in a substrate, and a second conductive area extending from a bottom of the trench, the second conductive area being electrically coupled to the first conductive area and spaced apart from the first conductive area; a storage node having a first conductive extension extending into a first dielectric space provided between the first conductive area and the second conductive area of the electrode, and a second conductive extension extending into a second dielectric space provided within the second conductive area of the electrode; and a dielectric layer electrically insulating the electrode from the storage node.

Abstract translation: 沟槽电容器包括电极，其具有形成在设置在基板中的沟槽中的第一导电区域和从沟槽的底部延伸的第二导电区域，第二导电区域电耦合到第一导电区域并与 第一导电区; 存储节点具有延伸到设置在电极的第一导电区域和第二导电区域之间的第一电介质空间的第一导电延伸部分，以及延伸到设置在电极的第二导电区域内的第二电介质空间的第二导电延伸部分; 以及将电极与存储节点电绝缘的电介质层。

公开(公告)号：US20050057998A1

公开(公告)日：2005-03-17

申请号：US10957688

申请日：2004-10-05

Applicant: Brian Lee ,  Chih-Yu Lee

Inventor： Brian Lee ,  Chih-Yu Lee

IPC: G03C5/00 ,  G03F1/00 ,  G03F9/00 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/32139 ,  G03F1/30 ,  H01L27/10861 ,  H01L27/10891

Abstract: An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.

Abstract translation: 具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。 掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。 通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

公开(公告)号：US06855610B2

公开(公告)日：2005-02-15

申请号：US10330522

申请日：2002-12-27

Applicant: Ming-Sheng Tung ,  Yueh-Chuan Lee

Inventor： Ming-Sheng Tung ,  Yueh-Chuan Lee

IPC: H01L21/336 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

Abstract translation: 用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。