公开(公告)号：US07320912B2

公开(公告)日：2008-01-22

申请号：US11125676

申请日：2005-05-10

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L21/8242

CPC分类号： H01L29/945 ,  H01L27/1087

摘要： A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

摘要翻译： 形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。 掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

公开(公告)号：US20060128157A1

公开(公告)日：2006-06-15

申请号：US11338679

申请日：2006-01-25

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L21/311 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823456 ,  H01L29/42376

摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.

摘要翻译： 具有部分蚀刻栅极的半导体结构及其制造方法。 具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层 结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。 此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层 被部分删除。

公开(公告)号：US20060255388A1

公开(公告)日：2006-11-16

申请号：US11125676

申请日：2005-05-10

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L29/772 ,  H01L27/108 ,  H01L21/8242 ,  H01L21/8232

CPC分类号： H01L29/945 ,  H01L27/1087

摘要： A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

摘要翻译： 形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。 掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

公开(公告)号：US07034354B2

公开(公告)日：2006-04-25

申请号：US10695739

申请日：2003-10-30

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L21/108

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823456 ,  H01L29/42376

摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.

摘要翻译： 具有部分蚀刻栅极的半导体结构及其制造方法。 具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层 结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。 此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层 被部分删除。

公开(公告)号：US20050127453A1

公开(公告)日：2005-06-16

申请号：US11041503

申请日：2005-01-21

申请人： Ming-Sheng Tung ,  Yueh-Chuan Lee

发明人： Ming-Sheng Tung ,  Yueh-Chuan Lee

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L23/485 ,  H01L21/8242 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

摘要翻译： 用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

公开(公告)号：US20050106844A1

公开(公告)日：2005-05-19

申请号：US10788807

申请日：2004-02-27

申请人： Ming-Sheng Tung ,  Yueh-Chuan Lee ,  Fang-Yu Yeh ,  Chi Lin

发明人： Ming-Sheng Tung ,  Yueh-Chuan Lee ,  Fang-Yu Yeh ,  Chi Lin

IPC分类号： H01L21/336 ,  H01L29/10

CPC分类号： H01L29/6653 ,  H01L29/1045 ,  H01L29/6659 ,  H01L29/66659

摘要： Ions are implanted into a substrate, using a gate and its sidewall liner on the substrate as the mask, to form a source/drain region in the substrate beneath the liner and adjacent to the two sides of the gate. The liner is etched to reduce its thickness. Then, ions are implanted into the substrate to form a halo doped region surrounding the source/drain region. The halo doped region is closer to the MOSFET channel region and overlaps less with the source/drain region. Therefore, the device threshold voltage can be sustained and the junction leakage can also be minimized.

摘要翻译： 将离子以植入基板上的栅极及其侧壁衬垫作为掩模注入到衬底中，以在衬底下面形成源极/漏极区域，并且邻近栅极的两侧。 蚀刻衬里以减小其厚度。 然后，将离子注入到衬底中以形成围绕源/漏区的卤素掺杂区。 卤素掺杂区域更靠近MOSFET沟道区域，并且与源极/漏极区域重叠较小。 因此，可以维持器件阈值电压，也可以最小化结漏电。

公开(公告)号：US06855610B2

公开(公告)日：2005-02-15

申请号：US10330522

申请日：2002-12-27

申请人： Ming-Sheng Tung ,  Yueh-Chuan Lee

发明人： Ming-Sheng Tung ,  Yueh-Chuan Lee

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

摘要翻译： 用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

公开(公告)号：US06821842B1

公开(公告)日：2004-11-23

申请号：US10708227

申请日：2004-02-18

申请人： Yueh-Chuan Lee ,  Shih-Lung Chen

发明人： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/10873 ,  H01L29/66181 ,  H01L29/945

摘要： A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

摘要翻译： 提供了一种动态随机存取存储器（DRAM）结构及其制造方法。 在制造过程中，在与隔离结构相邻的部分中，沟道区域形成有与衬底相同的导电性的掺杂区域。 通过在形成沟槽之后但在有源区的定义之前，通过在邻近沟道区的电容器沟槽的上部通过进行倾斜注入而将离子注入到衬底中来形成掺杂区。

公开(公告)号：US06680237B2

公开(公告)日：2004-01-20

申请号：US09967709

申请日：2001-09-27

申请人： Shih-Lung Chen ,  Hsiao-Lei Wang ,  Hwei-Lin Chuang ,  Yueh-Chuan Lee

发明人： Shih-Lung Chen ,  Hsiao-Lei Wang ,  Hwei-Lin Chuang ,  Yueh-Chuan Lee

IPC分类号： H01L2120

CPC分类号： H01L27/10867

摘要： A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.

摘要翻译： 一种制造深沟槽电容器的方法。 在衬底中形成深沟槽。 依次形成保形电容器电介质层和第一导电层，完全填充深沟槽。 第一导电层具有接缝。 蚀刻第一导电层以打开接缝。 在深沟槽的内表面上形成环状氧化物层。 在深沟槽内部的轴环氧化物层上方形成轴环衬层。 使用套环内层作为掩模，去除第一导电层上方和接缝内的环氧化物材料。 衣领衬里层被去除。 最后，在深沟槽内依次形成第二导电层和第三导电层。

公开(公告)号：US06903029B2

公开(公告)日：2005-06-07

申请号：US10893263

申请日：2004-07-19

申请人： Ching-Fa Yeh ,  Yueh-Chuan Lee ,  Chih-Chuan Hsu ,  Kwo-Hau Wu ,  Shuo-Cheng Wang

发明人： Ching-Fa Yeh ,  Yueh-Chuan Lee ,  Chih-Chuan Hsu ,  Kwo-Hau Wu ,  Shuo-Cheng Wang

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76801 ,  H01L21/02131 ,  H01L21/02137 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/3122 ,  H01L21/316 ,  H01L21/31629 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  Y10T428/265

摘要： The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.

摘要翻译： 本发明提供一种通过形成夹层电介质结构来减小厚的自旋电介质层的应力的技术，其中通过旋涂形成在基板上的第一介电层，形成液相沉积（LPD）二氧化硅层 第一电介质层，并且通过旋涂在LPD二氧化硅层上形成第二电介质层。 可以进一步对LPD二氧化硅层进行氮等离子体处理，以提高其热稳定性和抗水渗透能力。