公开(公告)号：US07320912B2

公开(公告)日：2008-01-22

申请号：US11125676

申请日：2005-05-10

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L21/8242

CPC分类号： H01L29/945 ,  H01L27/1087

摘要： A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

摘要翻译： 形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。 掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

公开(公告)号：US20060255388A1

公开(公告)日：2006-11-16

申请号：US11125676

申请日：2005-05-10

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L29/772 ,  H01L27/108 ,  H01L21/8242 ,  H01L21/8232

CPC分类号： H01L29/945 ,  H01L27/1087

摘要： A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

摘要翻译： 形成沟槽电容器的方法包括：去除衬底的一部分以在衬底内形成沟槽; 在衬底内的掩埋隔离层处形成; 在所述衬底中至少在围绕所述沟槽的下部的区域中在所述沟槽电容器中形成第一电极; 形成沟槽电容器的电介质层; 以及在所述沟槽中形成所述沟槽电容器的第二电极。 掩埋隔离层与沟槽相交并且具有一个或多个间隙，用于在掩埋隔离层之上的第一衬底区域和掩埋隔离层下面的第二衬底区域之间提供身体接触。

公开(公告)号：US07034354B2

公开(公告)日：2006-04-25

申请号：US10695739

申请日：2003-10-30

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L21/108

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823456 ,  H01L29/42376

摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.

摘要翻译： 具有部分蚀刻栅极的半导体结构及其制造方法。 具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层 结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。 此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层 被部分删除。

公开(公告)号：US20050127453A1

公开(公告)日：2005-06-16

申请号：US11041503

申请日：2005-01-21

申请人： Ming-Sheng Tung ,  Yueh-Chuan Lee

发明人： Ming-Sheng Tung ,  Yueh-Chuan Lee

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L23/485 ,  H01L21/8242 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

摘要翻译： 用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

公开(公告)号：US20050106844A1

公开(公告)日：2005-05-19

申请号：US10788807

申请日：2004-02-27

申请人： Ming-Sheng Tung ,  Yueh-Chuan Lee ,  Fang-Yu Yeh ,  Chi Lin

发明人： Ming-Sheng Tung ,  Yueh-Chuan Lee ,  Fang-Yu Yeh ,  Chi Lin

IPC分类号： H01L21/336 ,  H01L29/10

CPC分类号： H01L29/6653 ,  H01L29/1045 ,  H01L29/6659 ,  H01L29/66659

摘要： Ions are implanted into a substrate, using a gate and its sidewall liner on the substrate as the mask, to form a source/drain region in the substrate beneath the liner and adjacent to the two sides of the gate. The liner is etched to reduce its thickness. Then, ions are implanted into the substrate to form a halo doped region surrounding the source/drain region. The halo doped region is closer to the MOSFET channel region and overlaps less with the source/drain region. Therefore, the device threshold voltage can be sustained and the junction leakage can also be minimized.

摘要翻译： 将离子以植入基板上的栅极及其侧壁衬垫作为掩模注入到衬底中，以在衬底下面形成源极/漏极区域，并且邻近栅极的两侧。 蚀刻衬里以减小其厚度。 然后，将离子注入到衬底中以形成围绕源/漏区的卤素掺杂区。 卤素掺杂区域更靠近MOSFET沟道区域，并且与源极/漏极区域重叠较小。 因此，可以维持器件阈值电压，也可以最小化结漏电。

公开(公告)号：US06855610B2

公开(公告)日：2005-02-15

申请号：US10330522

申请日：2002-12-27

申请人： Ming-Sheng Tung ,  Yueh-Chuan Lee

发明人： Ming-Sheng Tung ,  Yueh-Chuan Lee

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

摘要翻译： 用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

公开(公告)号：US20060128157A1

公开(公告)日：2006-06-15

申请号：US11338679

申请日：2006-01-25

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L21/311 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823456 ,  H01L29/42376

摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.

摘要翻译： 具有部分蚀刻栅极的半导体结构及其制造方法。 具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层 结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。 此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层 被部分删除。

公开(公告)号：US20070090409A1

公开(公告)日：2007-04-26

申请号：US11258119

申请日：2005-10-26

申请人： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

发明人： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L27/105 ,  H01L21/823456 ,  H01L27/1052

摘要： The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.

摘要翻译： 本发明涉及一种半导体器件，其分别包括位于衬底的存储器阵列区域和外围电路区域中的至少一个栅极，其中存储器阵列区域中的图案密度高于外围电路区域中的图案密度 。 半导体器件还包括位于存储器阵列区域和外围电路区域中的阻挡层，位于外围电路区域中的阻挡层上的未掺杂的氧化物屏障和含硼硅酸盐玻璃，其中 位于存储器阵列区域中的阻挡层上和外围电路区域中未掺杂的氧化物屏障上。

公开(公告)号：US20130257396A1

公开(公告)日：2013-10-03

申请号：US13434856

申请日：2012-03-30

申请人： Ming-Sheng Tung

发明人： Ming-Sheng Tung

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.

摘要翻译： 带隙基准电路包括第一电路，第二电路和第三电路。 第一电路用于根据第一参考电压产生第一电流和第一电压。 第二电路耦合到第一电路，用于根据第一电压产生第二电压。 第三电路耦合到第一电路和第二电路，用于根据第一电流产生电压偏移，并根据第二电压和电压偏移产生带隙基准电压。 第一电路和第二电路相互补充以抵消由于温度变化引起的带隙参考电压的变化。

公开(公告)号：US08698479B2

公开(公告)日：2014-04-15

申请号：US13434856

申请日：2012-03-30

申请人： Ming-Sheng Tung

发明人： Ming-Sheng Tung

IPC分类号： G05F3/08 ,  H01L37/00

CPC分类号： G05F3/30

摘要： A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.

摘要翻译： 带隙基准电路包括第一电路，第二电路和第三电路。 第一电路用于根据第一参考电压产生第一电流和第一电压。 第二电路耦合到第一电路，用于根据第一电压产生第二电压。 第三电路耦合到第一电路和第二电路，用于根据第一电流产生电压偏移，并根据第二电压和电压偏移产生带隙基准电压。 第一电路和第二电路相互补充以抵消由于温度变化引起的带隙参考电压的变化。