公开(公告)号：US20240381661A1

公开(公告)日：2024-11-14

申请号：US18659356

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Riccardo Pazzocco ,  Giorgio Servalli ,  Marcello Mariani

IPC: H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A variety of applications can include apparatus having a memory device with ferroelectric capacitors as storage structures in memory cells. A ferroelectric capacitor can have a bottom electrode, a top electrode, and ferroelectric material, where a leaker electrically couples the bottom electrode to the top electrode. Conductive plates can be positioned on and contacting a different set of the memory cells. The plates can be separated from each other along a direction parallel to an access line to the array, without dummy memory cells between the different sets of memory cells at the edges of the plates. A number of different fabrication options can be implemented to realize a memory array with container structures that can have small container spacing without dummy memory cells at the edges of plate cuts. The different fabrication options can be realized by differences in process related to top electrode formation.

公开(公告)号：US20240381628A1

公开(公告)日：2024-11-14

申请号：US18659367

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Anthony J. Kanago

IPC: H10B12/00

Abstract: A variety of applications can include a memory device having a memory array region on a memory die and a periphery to the memory array region on the memory die, where the periphery can include a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) device. A metal shield can be integrated in the memory array region, where the metal shield is structured as a shield to digit lines of the memory array. A metal body plate in the periphery can be structured as a back gate to the FDSOI CMOS device.

公开(公告)号：US20240379596A1

公开(公告)日：2024-11-14

申请号：US18660210

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Terrence B. McDaniel ,  Kunal R. Parekh ,  Bret K. Street ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A through via extends entirely through the substrate. The through via includes a protruding portion that extends beyond the back side of the substrate. A layer of silicon carbon nitride is disposed at the back side of the substrate and along sidewalls of the protruding portion of the through via. A layer of oxide is disposed at the back side of the substrate and at least partially surrounding the protruding portion of the through via. A conductive pad is disposed at a coupling surface of the through via and at least partially extending through the layer of oxide. As a result, a reliable and cost-efficient semiconductor device can be assembled.

公开(公告)号：US20240379568A1

公开(公告)日：2024-11-14

申请号：US18780253

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/538 ,  G11C5/02 ,  G11C5/06 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

公开(公告)号：US20240378156A1

公开(公告)日：2024-11-14

申请号：US18779666

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

IPC: G06F12/0891

Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a cache storage of the memory device.

公开(公告)号：US20240378111A1

公开(公告)日：2024-11-14

申请号：US18641290

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Jonathan R. Hinkle ,  Luca Bert

IPC: G06F11/10

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems are described. The grouped set of chained subsystems may coordinate internal communications and operations across the separate subsystems within the set. Memory locations for related or connected data may be dynamically computed to be across multiple subsystems to allow for parallel processing, failure/error recovery, or the like.

公开(公告)号：US20240377982A1

公开(公告)日：2024-11-14

申请号：US18660089

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Minjian Wu

IPC: G06F3/06 ,  B60R16/023 ,  B60R16/033

Abstract: Exemplary methods, apparatuses, and systems include a communication port manager for controlling communication of sensor data. The communication port manager receives a set of sensor data from a plurality of data sensors of a vehicle management system of a vehicle. The communication port manager writes the set of sensor data to memory of the memory subsystem. The communication port manager receives, from a battery management system, a request to read the sensor data. The communication port manager sends the set of sensor data to the battery management system, wherein the battery management system uses a wireless connection to send the sensor data to a cloud system.

公开(公告)号：US20240377964A1

公开(公告)日：2024-11-14

申请号：US18641296

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Jonathan R. Hinkle ,  Luca Bert

IPC: G06F3/06

Abstract: Methods, apparatuses, and systems related to serially chained memory subsystems that support and provide redundant coverage for multiple hosts are described. The grouped set of chained subsystems can provide dedicated storage locations for each of the multiple hosts during normal operations. When one of the hosts fail, the grouped set can reconfigure the internal accessing scheme, thereby allowing the surviving host to see and access locations and data that was initially assigned to the failed host.

公开(公告)号：US12142708B2

公开(公告)日：2024-11-12

申请号：US18340644

申请日：2023-06-23

Applicant: Micron Technology, Inc.

Inventor： Martin F. Schubert ,  Vladimir Odnoblyudov

IPC: H01L33/38 ,  H01L33/00 ,  H01L33/06 ,  H01L33/36 ,  H01L33/40 ,  H01L33/42 ,  H01L33/62

Abstract: Various embodiments of light emitting dies and solid state lighting (“SSL”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an SSL structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the SSL structure, and a second electrode spaced apart from the first electrode of the SSL structure. The first and second electrode are configured to receive the applied electrical voltage. Both the first and second electrodes are accessible from the same side of the SSL structure via wirebonding.

公开(公告)号：US12142680B2

公开(公告)日：2024-11-12

申请号：US17317636

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Hong Li ,  Erica L. Poelstra

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/49 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H10B12/00 ,  H10B63/00 ,  H01L21/764

Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.