公开(公告)号：US11115179B2

公开(公告)日：2021-09-07

申请号：US17000182

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Bret G. Stott ,  Craig E. Hampel ,  Frederick A. Ware

IPC: H04L7/033 ,  H04L7/00 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  H03L7/081 ,  H04L1/20 ,  G11C7/04

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

公开(公告)号：US11100976B2

公开(公告)日：2021-08-24

申请号：US16897157

申请日：2020-06-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G06F1/10 ,  G11C11/409 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18

Abstract: An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.

公开(公告)号：US11080185B2

公开(公告)日：2021-08-03

申请号：US16618105

申请日：2018-05-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/00 ,  G06F12/0802

Abstract: A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

公开(公告)号：US20210200680A1

公开(公告)日：2021-07-01

申请号：US17058492

申请日：2019-05-31

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Frederick A. Ware ,  Michael Raymond Miller ,  Collins Williams

IPC: G06F12/0864

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

公开(公告)号：US20210174863A1

公开(公告)日：2021-06-10

申请号：US17101574

申请日：2020-11-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C29/52 ,  G11C7/02 ,  G11C11/4096 ,  G06F11/10 ,  G11C29/04

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20210174862A1

公开(公告)日：2021-06-10

申请号：US17100850

申请日：2020-11-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  James E. Harris

IPC: G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  G11C7/22

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

公开(公告)号：US20210173737A1

公开(公告)日：2021-06-10

申请号：US16768722

申请日：2018-11-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0882

Abstract: A hybrid volatile/non-volatile memory employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). The memory supports error-detection and correction (EDC) techniques by allocating a fraction of DRAM storage to information calculated for each unit of stored data that can be used to detect and correct errors. An interface between the DRAM cache and NVM executes a wear-leveling scheme that aggregates and distributes NVM data and EDC write operations in a manner that prolongs service life.

公开(公告)号：US11029216B1

公开(公告)日：2021-06-08

申请号：US16528496

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Frederick A. Ware

IPC: H03K19/0175 ,  G05F1/56 ,  G01K7/01 ,  G05F3/24

Abstract: During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage.

公开(公告)号：US11025274B2

公开(公告)日：2021-06-01

申请号：US16690764

申请日：2019-11-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03M13/05 ,  G06F11/10 ,  G06F13/16 ,  G06F3/06 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15 ,  H03M13/19

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

公开(公告)号：US11024362B2

公开(公告)日：2021-06-01

申请号：US16657658

申请日：2019-10-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/4076 ,  G11C11/408 ,  G11C5/04 ,  G11C11/4093 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.