公开(公告)号：US20230018166A1

公开(公告)日：2023-01-19

申请号：US17853315

申请日：2022-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

IPC: G11C11/56 ,  G11C11/16 ,  G06N3/06 ,  G11C11/4074 ,  G06F17/16

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

公开(公告)号：US20220398444A1

公开(公告)日：2022-12-15

申请号：US17893071

申请日：2022-08-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Steven LEMKE ,  Nha NGUYEN ,  Vipin TIWARI ,  Nhan DO

IPC: G06N3/063 ,  G06N3/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming an analog neural non-volatile memory cell in an array to a target value representing one of N different values, where N is an integer; verifying that a value stored in the analog neural non-volatile memory cell is within an acceptable window of values around the target value; repeating the programming and verifying for each of the N values; and identifying the analog neural non-volatile memory cell as bad if any of the verifying indicates a value stored in the cell outside of the acceptable window of values around the target value.

公开(公告)号：US20220392549A1

公开(公告)日：2022-12-08

申请号：US17482095

申请日：2021-09-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  ALEXANDER KOTOV

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2. For each memory cell group, the method includes programming each of the non-volatile memory cells in the memory cell group to a particular program state, performing multiple read operations on each of the non-volatile memory cells in the memory cell group, identifying one of the non-volatile memory cells in the memory cell group that exhibits a lowest read variance during the multiple read operations, deeply programming all of the non-volatile memory cells in the memory cell group except the identified non-volatile memory cell, and programming the identified non-volatile memory cell in the memory cell group with user data.

公开(公告)号：US11521683B2

公开(公告)日：2022-12-06

申请号：US17191392

申请日：2021-03-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US11521682B2

公开(公告)日：2022-12-06

申请号：US17095661

申请日：2020-11-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G11C7/04

Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.

公开(公告)号：US20220374161A1

公开(公告)日：2022-11-24

申请号：US17463063

申请日：2021-08-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Mark Reiten

IPC: G06F3/06 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network. In some embodiments, an output block receives current from a W+ bit line and current from an associated W− bit line, and the output block generates an output signal that is a differential signal in certain embodiments and is a single ended signal in other embodiments.

公开(公告)号：US11507816B2

公开(公告)日：2022-11-22

申请号：US16576533

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G06F17/16 ,  G11C11/54 ,  G11C11/56

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20220336020A1

公开(公告)日：2022-10-20

申请号：US17850447

申请日：2022-06-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Steven Lemke ,  Hieu Van Tran ,  Yuri Tkachev ,  Louisa Schneider ,  Henry A. Om'mani ,  Thuan Vu ,  Nhan Do ,  Vipin Tiwari

IPC: G11C16/10 ,  G06N3/063 ,  G11C16/26 ,  G11C16/14

Abstract: Examples for ultra-precise tuning of a selected memory cell are disclosed. In one example, a method of programming a first memory cell in a neural memory to a target value is disclosed, the method comprising programming a second memory cell by applying programming voltages to terminals of the second memory cell; and determining if an output of the first memory cell has reached the target value.

公开(公告)号：US20220320125A1

公开(公告)日：2022-10-06

申请号：US17845782

申请日：2022-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: H01L27/11526 ,  H01L27/11519 ,  H01L27/11521 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  H01L29/423 ,  H01L29/788

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

公开(公告)号：US11444091B2

公开(公告)日：2022-09-13

申请号：US17129865

申请日：2020-12-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jack Sun ,  Chunming Wang ,  Xian Liu ,  Andy Yang ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: H01L21/00 ,  H01L27/11531 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11529

Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material.